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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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2066aadd53
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
are flagged as __cpuinit -- so if we remove the __cpuinit from
arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
content into no-ops as early as possible, since that will get rid
of these warnings. In any case, they are temporary and harmless.
This removes all the arch/sparc uses of the __cpuinit macros from
C files and removes __CPUINIT from assembly files. Note that even
though arch/sparc/kernel/trampoline_64.S has instances of ".previous"
in it, they are all paired off against explicit ".section" directives,
and not implicitly paired with __CPUINIT (unlike mips and arm were).
[1] https://lkml.org/lkml/2013/5/20/589
Cc: "David S. Miller" <davem@davemloft.net>
Cc: sparclinux@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
415 lines
9.1 KiB
ArmAsm
415 lines
9.1 KiB
ArmAsm
/*
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* trampoline.S: Jump start slave processors on sparc64.
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*
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* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
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*/
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#include <linux/init.h>
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#include <asm/head.h>
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#include <asm/asi.h>
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#include <asm/lsu.h>
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#include <asm/dcr.h>
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#include <asm/dcu.h>
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#include <asm/pstate.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/spitfire.h>
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#include <asm/processor.h>
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#include <asm/thread_info.h>
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#include <asm/mmu.h>
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#include <asm/hypervisor.h>
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#include <asm/cpudata.h>
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.data
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.align 8
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call_method:
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.asciz "call-method"
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.align 8
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itlb_load:
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.asciz "SUNW,itlb-load"
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.align 8
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dtlb_load:
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.asciz "SUNW,dtlb-load"
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#define TRAMP_STACK_SIZE 1024
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.align 16
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tramp_stack:
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.skip TRAMP_STACK_SIZE
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.align 8
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.globl sparc64_cpu_startup, sparc64_cpu_startup_end
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sparc64_cpu_startup:
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BRANCH_IF_SUN4V(g1, niagara_startup)
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BRANCH_IF_CHEETAH_BASE(g1, g5, cheetah_startup)
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BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1, g5, cheetah_plus_startup)
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ba,pt %xcc, spitfire_startup
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nop
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cheetah_plus_startup:
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/* Preserve OBP chosen DCU and DCR register settings. */
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ba,pt %xcc, cheetah_generic_startup
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nop
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cheetah_startup:
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mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
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wr %g1, %asr18
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sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
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or %g5, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
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sllx %g5, 32, %g5
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or %g5, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g5
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stxa %g5, [%g0] ASI_DCU_CONTROL_REG
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membar #Sync
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/* fallthru */
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cheetah_generic_startup:
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mov TSB_EXTENSION_P, %g3
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stxa %g0, [%g3] ASI_DMMU
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stxa %g0, [%g3] ASI_IMMU
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membar #Sync
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mov TSB_EXTENSION_S, %g3
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stxa %g0, [%g3] ASI_DMMU
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membar #Sync
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mov TSB_EXTENSION_N, %g3
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stxa %g0, [%g3] ASI_DMMU
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stxa %g0, [%g3] ASI_IMMU
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membar #Sync
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/* fallthru */
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niagara_startup:
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/* Disable STICK_INT interrupts. */
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sethi %hi(0x80000000), %g5
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sllx %g5, 32, %g5
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wr %g5, %asr25
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ba,pt %xcc, startup_continue
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nop
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spitfire_startup:
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mov (LSU_CONTROL_IC | LSU_CONTROL_DC | LSU_CONTROL_IM | LSU_CONTROL_DM), %g1
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stxa %g1, [%g0] ASI_LSU_CONTROL
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membar #Sync
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startup_continue:
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mov %o0, %l0
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BRANCH_IF_SUN4V(g1, niagara_lock_tlb)
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sethi %hi(0x80000000), %g2
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sllx %g2, 32, %g2
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wr %g2, 0, %tick_cmpr
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/* Call OBP by hand to lock KERNBASE into i/d tlbs.
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* We lock 'num_kernel_image_mappings' consequetive entries.
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*/
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sethi %hi(prom_entry_lock), %g2
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1: ldstub [%g2 + %lo(prom_entry_lock)], %g1
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brnz,pn %g1, 1b
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nop
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sethi %hi(p1275buf), %g2
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or %g2, %lo(p1275buf), %g2
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ldx [%g2 + 0x10], %l2
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add %l2, -(192 + 128), %sp
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flushw
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/* Setup the loop variables:
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* %l3: VADDR base
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* %l4: TTE base
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* %l5: Loop iterator, iterates from 0 to 'num_kernel_image_mappings'
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* %l6: Number of TTE entries to map
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* %l7: Highest TTE entry number, we count down
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*/
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sethi %hi(KERNBASE), %l3
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sethi %hi(kern_locked_tte_data), %l4
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ldx [%l4 + %lo(kern_locked_tte_data)], %l4
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clr %l5
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sethi %hi(num_kernel_image_mappings), %l6
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lduw [%l6 + %lo(num_kernel_image_mappings)], %l6
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add %l6, 1, %l6
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mov 15, %l7
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BRANCH_IF_ANY_CHEETAH(g1,g5,2f)
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mov 63, %l7
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2:
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3:
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/* Lock into I-MMU */
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sethi %hi(call_method), %g2
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or %g2, %lo(call_method), %g2
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stx %g2, [%sp + 2047 + 128 + 0x00]
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mov 5, %g2
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stx %g2, [%sp + 2047 + 128 + 0x08]
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mov 1, %g2
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stx %g2, [%sp + 2047 + 128 + 0x10]
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sethi %hi(itlb_load), %g2
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or %g2, %lo(itlb_load), %g2
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stx %g2, [%sp + 2047 + 128 + 0x18]
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sethi %hi(prom_mmu_ihandle_cache), %g2
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lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
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stx %g2, [%sp + 2047 + 128 + 0x20]
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/* Each TTE maps 4MB, convert index to offset. */
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sllx %l5, 22, %g1
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add %l3, %g1, %g2
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stx %g2, [%sp + 2047 + 128 + 0x28] ! VADDR
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add %l4, %g1, %g2
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stx %g2, [%sp + 2047 + 128 + 0x30] ! TTE
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/* TTE index is highest minus loop index. */
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sub %l7, %l5, %g2
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stx %g2, [%sp + 2047 + 128 + 0x38]
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sethi %hi(p1275buf), %g2
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or %g2, %lo(p1275buf), %g2
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ldx [%g2 + 0x08], %o1
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call %o1
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add %sp, (2047 + 128), %o0
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/* Lock into D-MMU */
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sethi %hi(call_method), %g2
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or %g2, %lo(call_method), %g2
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stx %g2, [%sp + 2047 + 128 + 0x00]
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mov 5, %g2
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stx %g2, [%sp + 2047 + 128 + 0x08]
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mov 1, %g2
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stx %g2, [%sp + 2047 + 128 + 0x10]
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sethi %hi(dtlb_load), %g2
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or %g2, %lo(dtlb_load), %g2
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stx %g2, [%sp + 2047 + 128 + 0x18]
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sethi %hi(prom_mmu_ihandle_cache), %g2
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lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
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stx %g2, [%sp + 2047 + 128 + 0x20]
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/* Each TTE maps 4MB, convert index to offset. */
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sllx %l5, 22, %g1
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add %l3, %g1, %g2
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stx %g2, [%sp + 2047 + 128 + 0x28] ! VADDR
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add %l4, %g1, %g2
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stx %g2, [%sp + 2047 + 128 + 0x30] ! TTE
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/* TTE index is highest minus loop index. */
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sub %l7, %l5, %g2
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stx %g2, [%sp + 2047 + 128 + 0x38]
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sethi %hi(p1275buf), %g2
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or %g2, %lo(p1275buf), %g2
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ldx [%g2 + 0x08], %o1
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call %o1
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add %sp, (2047 + 128), %o0
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add %l5, 1, %l5
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cmp %l5, %l6
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bne,pt %xcc, 3b
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nop
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sethi %hi(prom_entry_lock), %g2
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stb %g0, [%g2 + %lo(prom_entry_lock)]
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ba,pt %xcc, after_lock_tlb
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nop
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niagara_lock_tlb:
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sethi %hi(KERNBASE), %l3
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sethi %hi(kern_locked_tte_data), %l4
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ldx [%l4 + %lo(kern_locked_tte_data)], %l4
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clr %l5
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sethi %hi(num_kernel_image_mappings), %l6
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lduw [%l6 + %lo(num_kernel_image_mappings)], %l6
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add %l6, 1, %l6
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1:
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mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
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sllx %l5, 22, %g2
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add %l3, %g2, %o0
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clr %o1
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add %l4, %g2, %o2
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mov HV_MMU_IMMU, %o3
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ta HV_FAST_TRAP
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mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
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sllx %l5, 22, %g2
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add %l3, %g2, %o0
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clr %o1
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add %l4, %g2, %o2
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mov HV_MMU_DMMU, %o3
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ta HV_FAST_TRAP
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add %l5, 1, %l5
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cmp %l5, %l6
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bne,pt %xcc, 1b
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nop
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after_lock_tlb:
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wrpr %g0, (PSTATE_PRIV | PSTATE_PEF), %pstate
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wr %g0, 0, %fprs
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wr %g0, ASI_P, %asi
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mov PRIMARY_CONTEXT, %g7
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661: stxa %g0, [%g7] ASI_DMMU
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.section .sun4v_1insn_patch, "ax"
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.word 661b
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stxa %g0, [%g7] ASI_MMU
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.previous
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membar #Sync
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mov SECONDARY_CONTEXT, %g7
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661: stxa %g0, [%g7] ASI_DMMU
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.section .sun4v_1insn_patch, "ax"
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.word 661b
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stxa %g0, [%g7] ASI_MMU
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.previous
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membar #Sync
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/* Everything we do here, until we properly take over the
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* trap table, must be done with extreme care. We cannot
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* make any references to %g6 (current thread pointer),
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* %g4 (current task pointer), or %g5 (base of current cpu's
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* per-cpu area) until we properly take over the trap table
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* from the firmware and hypervisor.
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*
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* Get onto temporary stack which is in the locked kernel image.
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*/
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sethi %hi(tramp_stack), %g1
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or %g1, %lo(tramp_stack), %g1
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add %g1, TRAMP_STACK_SIZE, %g1
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sub %g1, STACKFRAME_SZ + STACK_BIAS + 256, %sp
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mov 0, %fp
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/* Put garbage in these registers to trap any access to them. */
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set 0xdeadbeef, %g4
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set 0xdeadbeef, %g5
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set 0xdeadbeef, %g6
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call init_irqwork_curcpu
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nop
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sethi %hi(tlb_type), %g3
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lduw [%g3 + %lo(tlb_type)], %g2
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cmp %g2, 3
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bne,pt %icc, 1f
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nop
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call hard_smp_processor_id
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nop
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call sun4v_register_mondo_queues
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nop
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1: call init_cur_cpu_trap
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ldx [%l0], %o0
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/* Start using proper page size encodings in ctx register. */
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sethi %hi(sparc64_kern_pri_context), %g3
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ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
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mov PRIMARY_CONTEXT, %g1
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661: stxa %g2, [%g1] ASI_DMMU
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.section .sun4v_1insn_patch, "ax"
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.word 661b
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stxa %g2, [%g1] ASI_MMU
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.previous
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membar #Sync
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wrpr %g0, 0, %wstate
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sethi %hi(prom_entry_lock), %g2
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1: ldstub [%g2 + %lo(prom_entry_lock)], %g1
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brnz,pn %g1, 1b
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nop
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/* As a hack, put &init_thread_union into %g6.
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* prom_world() loads from here to restore the %asi
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* register.
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*/
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sethi %hi(init_thread_union), %g6
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or %g6, %lo(init_thread_union), %g6
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sethi %hi(is_sun4v), %o0
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lduw [%o0 + %lo(is_sun4v)], %o0
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brz,pt %o0, 2f
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nop
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TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
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add %g2, TRAP_PER_CPU_FAULT_INFO, %g2
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stxa %g2, [%g0] ASI_SCRATCHPAD
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/* Compute physical address:
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*
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* paddr = kern_base + (mmfsa_vaddr - KERNBASE)
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*/
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sethi %hi(KERNBASE), %g3
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sub %g2, %g3, %g2
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sethi %hi(kern_base), %g3
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ldx [%g3 + %lo(kern_base)], %g3
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add %g2, %g3, %o1
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sethi %hi(sparc64_ttable_tl0), %o0
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set prom_set_trap_table_name, %g2
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stx %g2, [%sp + 2047 + 128 + 0x00]
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mov 2, %g2
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stx %g2, [%sp + 2047 + 128 + 0x08]
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mov 0, %g2
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stx %g2, [%sp + 2047 + 128 + 0x10]
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stx %o0, [%sp + 2047 + 128 + 0x18]
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stx %o1, [%sp + 2047 + 128 + 0x20]
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sethi %hi(p1275buf), %g2
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or %g2, %lo(p1275buf), %g2
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ldx [%g2 + 0x08], %o1
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call %o1
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add %sp, (2047 + 128), %o0
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ba,pt %xcc, 3f
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nop
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2: sethi %hi(sparc64_ttable_tl0), %o0
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set prom_set_trap_table_name, %g2
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stx %g2, [%sp + 2047 + 128 + 0x00]
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mov 1, %g2
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stx %g2, [%sp + 2047 + 128 + 0x08]
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mov 0, %g2
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stx %g2, [%sp + 2047 + 128 + 0x10]
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stx %o0, [%sp + 2047 + 128 + 0x18]
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sethi %hi(p1275buf), %g2
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or %g2, %lo(p1275buf), %g2
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ldx [%g2 + 0x08], %o1
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call %o1
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add %sp, (2047 + 128), %o0
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3: sethi %hi(prom_entry_lock), %g2
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stb %g0, [%g2 + %lo(prom_entry_lock)]
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ldx [%l0], %g6
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ldx [%g6 + TI_TASK], %g4
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mov 1, %g5
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sllx %g5, THREAD_SHIFT, %g5
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sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5
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add %g6, %g5, %sp
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mov 0, %fp
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rdpr %pstate, %o1
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or %o1, PSTATE_IE, %o1
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wrpr %o1, 0, %pstate
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call smp_callin
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nop
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call cpu_panic
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nop
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1: b,a,pt %xcc, 1b
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.align 8
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sparc64_cpu_startup_end:
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