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a4192d32ae
Otherwise we get the following error with omap3_defconfig and CONFIG_SMP: Error: selected processor does not support `sev' Signed-off-by: Tony Lindgren <tony@atomide.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
48 lines
1.1 KiB
C
48 lines
1.1 KiB
C
/*
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* OMAP4 machine specific smp.h
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*
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* Copyright (C) 2009 Texas Instruments, Inc.
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*
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* Author:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* Interface functions needed for the SMP. This file is based on arm
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* realview smp platform.
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* Copyright (c) 2003 ARM Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef OMAP_ARCH_SMP_H
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#define OMAP_ARCH_SMP_H
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#include <asm/hardware/gic.h>
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/* Needed for secondary core boot */
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extern void omap_secondary_startup(void);
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extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
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extern void omap_auxcoreboot_addr(u32 cpu_addr);
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extern u32 omap_read_auxcoreboot0(void);
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/*
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* We use Soft IRQ1 as the IPI
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*/
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static inline void smp_cross_call(const struct cpumask *mask)
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{
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gic_raise_softirq(mask, 1);
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}
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/*
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* Read MPIDR: Multiprocessor affinity register
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*/
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#define hard_smp_processor_id() \
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({ \
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unsigned int cpunum; \
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__asm__("mrc p15, 0, %0, c0, c0, 5" \
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: "=r" (cpunum)); \
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cpunum &= 0x0F; \
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})
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#endif
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