mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 23:40:55 +07:00
c0da085ad2
Patch from Catalin Marinas This patch adds PCI support for the Versatile PB926 platform. Signed-off-by: Colin King Signed-off-by: Catalin Marinas Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
530 lines
24 KiB
C
530 lines
24 KiB
C
/*
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* linux/include/asm-arm/arch-versatile/platform.h
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*
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* Copyright (c) ARM Limited 2003. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __address_h
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#define __address_h 1
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/*
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* Memory definitions
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*/
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#define VERSATILE_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)...*/
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#define VERSATILE_BOOT_ROM_HI 0x30000000
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#define VERSATILE_BOOT_ROM_BASE VERSATILE_BOOT_ROM_HI /* Normal position */
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#define VERSATILE_BOOT_ROM_SIZE SZ_64M
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#define VERSATILE_SSRAM_BASE /* VERSATILE_SSMC_BASE ? */
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#define VERSATILE_SSRAM_SIZE SZ_2M
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#define VERSATILE_FLASH_BASE 0x34000000
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#define VERSATILE_FLASH_SIZE SZ_64M
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/*
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* SDRAM
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*/
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#define VERSATILE_SDRAM_BASE 0x00000000
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/*
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* Logic expansion modules
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*
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*/
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/* ------------------------------------------------------------------------
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* Versatile Registers
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* ------------------------------------------------------------------------
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*
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*/
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#define VERSATILE_SYS_ID_OFFSET 0x00
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#define VERSATILE_SYS_SW_OFFSET 0x04
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#define VERSATILE_SYS_LED_OFFSET 0x08
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#define VERSATILE_SYS_OSC0_OFFSET 0x0C
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#if defined(CONFIG_ARCH_VERSATILE_PB)
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#define VERSATILE_SYS_OSC1_OFFSET 0x10
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#define VERSATILE_SYS_OSC2_OFFSET 0x14
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#define VERSATILE_SYS_OSC3_OFFSET 0x18
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#define VERSATILE_SYS_OSC4_OFFSET 0x1C
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#elif defined(CONFIG_MACH_VERSATILE_AB)
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#define VERSATILE_SYS_OSC1_OFFSET 0x1C
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#endif
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#define VERSATILE_SYS_LOCK_OFFSET 0x20
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#define VERSATILE_SYS_100HZ_OFFSET 0x24
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#define VERSATILE_SYS_CFGDATA1_OFFSET 0x28
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#define VERSATILE_SYS_CFGDATA2_OFFSET 0x2C
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#define VERSATILE_SYS_FLAGS_OFFSET 0x30
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#define VERSATILE_SYS_FLAGSSET_OFFSET 0x30
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#define VERSATILE_SYS_FLAGSCLR_OFFSET 0x34
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#define VERSATILE_SYS_NVFLAGS_OFFSET 0x38
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#define VERSATILE_SYS_NVFLAGSSET_OFFSET 0x38
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#define VERSATILE_SYS_NVFLAGSCLR_OFFSET 0x3C
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#define VERSATILE_SYS_RESETCTL_OFFSET 0x40
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#define VERSATILE_SYS_PCICTL_OFFSET 0x44
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#define VERSATILE_SYS_MCI_OFFSET 0x48
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#define VERSATILE_SYS_FLASH_OFFSET 0x4C
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#define VERSATILE_SYS_CLCD_OFFSET 0x50
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#define VERSATILE_SYS_CLCDSER_OFFSET 0x54
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#define VERSATILE_SYS_BOOTCS_OFFSET 0x58
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#define VERSATILE_SYS_24MHz_OFFSET 0x5C
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#define VERSATILE_SYS_MISC_OFFSET 0x60
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#define VERSATILE_SYS_TEST_OSC0_OFFSET 0x80
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#define VERSATILE_SYS_TEST_OSC1_OFFSET 0x84
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#define VERSATILE_SYS_TEST_OSC2_OFFSET 0x88
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#define VERSATILE_SYS_TEST_OSC3_OFFSET 0x8C
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#define VERSATILE_SYS_TEST_OSC4_OFFSET 0x90
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#define VERSATILE_SYS_BASE 0x10000000
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#define VERSATILE_SYS_ID (VERSATILE_SYS_BASE + VERSATILE_SYS_ID_OFFSET)
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#define VERSATILE_SYS_SW (VERSATILE_SYS_BASE + VERSATILE_SYS_SW_OFFSET)
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#define VERSATILE_SYS_LED (VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET)
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#define VERSATILE_SYS_OSC0 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC0_OFFSET)
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#define VERSATILE_SYS_OSC1 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC1_OFFSET)
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#if defined(CONFIG_ARCH_VERSATILE_PB)
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#define VERSATILE_SYS_OSC2 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC2_OFFSET)
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#define VERSATILE_SYS_OSC3 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC3_OFFSET)
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#define VERSATILE_SYS_OSC4 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC4_OFFSET)
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#endif
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#define VERSATILE_SYS_LOCK (VERSATILE_SYS_BASE + VERSATILE_SYS_LOCK_OFFSET)
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#define VERSATILE_SYS_100HZ (VERSATILE_SYS_BASE + VERSATILE_SYS_100HZ_OFFSET)
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#define VERSATILE_SYS_CFGDATA1 (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA1_OFFSET)
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#define VERSATILE_SYS_CFGDATA2 (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA2_OFFSET)
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#define VERSATILE_SYS_FLAGS (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGS_OFFSET)
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#define VERSATILE_SYS_FLAGSSET (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSSET_OFFSET)
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#define VERSATILE_SYS_FLAGSCLR (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSCLR_OFFSET)
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#define VERSATILE_SYS_NVFLAGS (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGS_OFFSET)
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#define VERSATILE_SYS_NVFLAGSSET (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSSET_OFFSET)
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#define VERSATILE_SYS_NVFLAGSCLR (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSCLR_OFFSET)
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#define VERSATILE_SYS_RESETCTL (VERSATILE_SYS_BASE + VERSATILE_SYS_RESETCTL_OFFSET)
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#define VERSATILE_SYS_PCICTL (VERSATILE_SYS_BASE + VERSATILE_SYS_PCICTL_OFFSET)
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#define VERSATILE_SYS_MCI (VERSATILE_SYS_BASE + VERSATILE_SYS_MCI_OFFSET)
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#define VERSATILE_SYS_FLASH (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
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#define VERSATILE_SYS_CLCD (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCD_OFFSET)
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#define VERSATILE_SYS_CLCDSER (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCDSER_OFFSET)
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#define VERSATILE_SYS_BOOTCS (VERSATILE_SYS_BASE + VERSATILE_SYS_BOOTCS_OFFSET)
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#define VERSATILE_SYS_24MHz (VERSATILE_SYS_BASE + VERSATILE_SYS_24MHz_OFFSET)
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#define VERSATILE_SYS_MISC (VERSATILE_SYS_BASE + VERSATILE_SYS_MISC_OFFSET)
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#define VERSATILE_SYS_TEST_OSC0 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC0_OFFSET)
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#define VERSATILE_SYS_TEST_OSC1 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC1_OFFSET)
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#define VERSATILE_SYS_TEST_OSC2 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC2_OFFSET)
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#define VERSATILE_SYS_TEST_OSC3 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC3_OFFSET)
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#define VERSATILE_SYS_TEST_OSC4 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC4_OFFSET)
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/*
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* Values for VERSATILE_SYS_RESET_CTRL
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*/
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#define VERSATILE_SYS_CTRL_RESET_CONFIGCLR 0x01
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#define VERSATILE_SYS_CTRL_RESET_CONFIGINIT 0x02
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#define VERSATILE_SYS_CTRL_RESET_DLLRESET 0x03
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#define VERSATILE_SYS_CTRL_RESET_PLLRESET 0x04
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#define VERSATILE_SYS_CTRL_RESET_POR 0x05
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#define VERSATILE_SYS_CTRL_RESET_DoC 0x06
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#define VERSATILE_SYS_CTRL_LED (1 << 0)
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/* ------------------------------------------------------------------------
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* Versatile control registers
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* ------------------------------------------------------------------------
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*/
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/*
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* VERSATILE_IDFIELD
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*
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* 31:24 = manufacturer (0x41 = ARM)
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* 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
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* 15:12 = FPGA (0x3 = XVC600 or XVC600E)
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* 11:4 = build value
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* 3:0 = revision number (0x1 = rev B (AHB))
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*/
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/*
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* VERSATILE_SYS_LOCK
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* control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL,
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* SYS_CLD, SYS_BOOTCS
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*/
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#define VERSATILE_SYS_LOCK_LOCKED (1 << 16)
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#define VERSATILE_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */
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/*
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* VERSATILE_SYS_FLASH
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*/
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#define VERSATILE_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */
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/*
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* VERSATILE_INTREG
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* - used to acknowledge and control MMCI and UART interrupts
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*/
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#define VERSATILE_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */
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#define VERSATILE_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */
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#define VERSATILE_INTREG_CARDIN 0x08 /* MMCI card in detect */
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/* write 1 to acknowledge and clear */
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#define VERSATILE_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */
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#define VERSATILE_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */
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/*
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* VERSATILE peripheral addresses
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*/
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#define VERSATILE_PCI_CORE_BASE 0x10001000 /* PCI core control */
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#define VERSATILE_I2C_BASE 0x10002000 /* I2C control */
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#define VERSATILE_SIC_BASE 0x10003000 /* Secondary interrupt controller */
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#define VERSATILE_AACI_BASE 0x10004000 /* Audio */
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#define VERSATILE_MMCI0_BASE 0x10005000 /* MMC interface */
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#define VERSATILE_KMI0_BASE 0x10006000 /* KMI interface */
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#define VERSATILE_KMI1_BASE 0x10007000 /* KMI 2nd interface */
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#define VERSATILE_CHAR_LCD_BASE 0x10008000 /* Character LCD */
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#define VERSATILE_UART3_BASE 0x10009000 /* UART 3 */
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#define VERSATILE_SCI1_BASE 0x1000A000
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#define VERSATILE_MMCI1_BASE 0x1000B000 /* MMC Interface */
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/* 0x1000C000 - 0x1000CFFF = reserved */
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#define VERSATILE_ETH_BASE 0x10010000 /* Ethernet */
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#define VERSATILE_USB_BASE 0x10020000 /* USB */
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/* 0x10030000 - 0x100FFFFF = reserved */
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#define VERSATILE_SMC_BASE 0x10100000 /* SMC */
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#define VERSATILE_MPMC_BASE 0x10110000 /* MPMC */
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#define VERSATILE_CLCD_BASE 0x10120000 /* CLCD */
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#define VERSATILE_DMAC_BASE 0x10130000 /* DMA controller */
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#define VERSATILE_VIC_BASE 0x10140000 /* Vectored interrupt controller */
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#define VERSATILE_PERIPH_BASE 0x10150000 /* off-chip peripherals alias from */
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/* 0x10000000 - 0x100FFFFF */
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#define VERSATILE_AHBM_BASE 0x101D0000 /* AHB monitor */
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#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
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#define VERSATILE_WATCHDOG_BASE 0x101E1000 /* Watchdog */
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#define VERSATILE_TIMER0_1_BASE 0x101E2000 /* Timer 0 and 1 */
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#define VERSATILE_TIMER2_3_BASE 0x101E3000 /* Timer 2 and 3 */
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#define VERSATILE_GPIO0_BASE 0x101E4000 /* GPIO port 0 */
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#define VERSATILE_GPIO1_BASE 0x101E5000 /* GPIO port 1 */
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#define VERSATILE_GPIO2_BASE 0x101E6000 /* GPIO port 2 */
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#define VERSATILE_GPIO3_BASE 0x101E7000 /* GPIO port 3 */
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#define VERSATILE_RTC_BASE 0x101E8000 /* Real Time Clock */
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/* 0x101E9000 - reserved */
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#define VERSATILE_SCI_BASE 0x101F0000 /* Smart card controller */
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#define VERSATILE_UART0_BASE 0x101F1000 /* Uart 0 */
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#define VERSATILE_UART1_BASE 0x101F2000 /* Uart 1 */
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#define VERSATILE_UART2_BASE 0x101F3000 /* Uart 2 */
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#define VERSATILE_SSP_BASE 0x101F4000 /* Synchronous Serial Port */
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#define VERSATILE_SSMC_BASE 0x20000000 /* SSMC */
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#define VERSATILE_IB2_BASE 0x24000000 /* IB2 module */
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#define VERSATILE_MBX_BASE 0x40000000 /* MBX */
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/* PCI space */
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#define VERSATILE_PCI_BASE 0x41000000 /* PCI Interface */
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#define VERSATILE_PCI_CFG_BASE 0x42000000
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#define VERSATILE_PCI_MEM_BASE0 0x44000000
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#define VERSATILE_PCI_MEM_BASE1 0x50000000
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#define VERSATILE_PCI_MEM_BASE2 0x60000000
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/* Sizes of above maps */
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#define VERSATILE_PCI_BASE_SIZE 0x01000000
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#define VERSATILE_PCI_CFG_BASE_SIZE 0x02000000
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#define VERSATILE_PCI_MEM_BASE0_SIZE 0x0c000000 /* 32Mb */
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#define VERSATILE_PCI_MEM_BASE1_SIZE 0x10000000 /* 256Mb */
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#define VERSATILE_PCI_MEM_BASE2_SIZE 0x10000000 /* 256Mb */
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#define VERSATILE_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */
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#define VERSATILE_LT_BASE 0x80000000 /* Logic Tile expansion */
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/*
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* Disk on Chip
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*/
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#define VERSATILE_DOC_BASE 0x2C000000
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#define VERSATILE_DOC_SIZE (16 << 20)
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#define VERSATILE_DOC_PAGE_SIZE 512
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#define VERSATILE_DOC_TOTAL_PAGES (DOC_SIZE / PAGE_SIZE)
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#define ERASE_UNIT_PAGES 32
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#define START_PAGE 0x80
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/*
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* LED settings, bits [7:0]
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*/
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#define VERSATILE_SYS_LED0 (1 << 0)
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#define VERSATILE_SYS_LED1 (1 << 1)
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#define VERSATILE_SYS_LED2 (1 << 2)
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#define VERSATILE_SYS_LED3 (1 << 3)
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#define VERSATILE_SYS_LED4 (1 << 4)
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#define VERSATILE_SYS_LED5 (1 << 5)
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#define VERSATILE_SYS_LED6 (1 << 6)
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#define VERSATILE_SYS_LED7 (1 << 7)
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#define ALL_LEDS 0xFF
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#define LED_BANK VERSATILE_SYS_LED
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/*
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* Control registers
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*/
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#define VERSATILE_IDFIELD_OFFSET 0x0 /* Versatile build information */
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#define VERSATILE_FLASHPROG_OFFSET 0x4 /* Flash devices */
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#define VERSATILE_INTREG_OFFSET 0x8 /* Interrupt control */
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#define VERSATILE_DECODE_OFFSET 0xC /* Fitted logic modules */
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/* ------------------------------------------------------------------------
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* Versatile Interrupt Controller - control registers
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* ------------------------------------------------------------------------
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*
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* Offsets from interrupt controller base
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*
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* System Controller interrupt controller base is
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*
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* VERSATILE_IC_BASE
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*
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* Core Module interrupt controller base is
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*
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* VERSATILE_SYS_IC
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*
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*/
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#define VIC_IRQ_STATUS 0
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#define VIC_FIQ_STATUS 0x04
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#define VIC_IRQ_RAW_STATUS 0x08
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#define VIC_INT_SELECT 0x0C /* 1 = FIQ, 0 = IRQ */
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#define VIC_IRQ_ENABLE 0x10 /* 1 = enable, 0 = disable */
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#define VIC_IRQ_ENABLE_CLEAR 0x14
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#define VIC_IRQ_SOFT 0x18
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#define VIC_IRQ_SOFT_CLEAR 0x1C
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#define VIC_PROTECT 0x20
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#define VIC_VECT_ADDR 0x30
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#define VIC_DEF_VECT_ADDR 0x34
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#define VIC_VECT_ADDR0 0x100 /* 0 to 15 */
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#define VIC_VECT_CNTL0 0x200 /* 0 to 15 */
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#define VIC_ITCR 0x300 /* VIC test control register */
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#define VIC_FIQ_RAW_STATUS 0x08
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#define VIC_FIQ_ENABLE 0x10 /* 1 = enable, 0 = disable */
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#define VIC_FIQ_ENABLE_CLEAR 0x14
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#define VIC_FIQ_SOFT 0x18
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#define VIC_FIQ_SOFT_CLEAR 0x1C
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#define SIC_IRQ_STATUS 0
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#define SIC_IRQ_RAW_STATUS 0x04
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#define SIC_IRQ_ENABLE 0x08
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#define SIC_IRQ_ENABLE_SET 0x08
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#define SIC_IRQ_ENABLE_CLEAR 0x0C
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#define SIC_INT_SOFT_SET 0x10
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#define SIC_INT_SOFT_CLEAR 0x14
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#define SIC_INT_PIC_ENABLE 0x20 /* read status of pass through mask */
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#define SIC_INT_PIC_ENABLES 0x20 /* set interrupt pass through bits */
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#define SIC_INT_PIC_ENABLEC 0x24 /* Clear interrupt pass through bits */
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#define VICVectCntl_Enable (1 << 5)
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/* ------------------------------------------------------------------------
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* Interrupts - bit assignment (primary)
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* ------------------------------------------------------------------------
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*/
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#define INT_WDOGINT 0 /* Watchdog timer */
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#define INT_SOFTINT 1 /* Software interrupt */
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#define INT_COMMRx 2 /* Debug Comm Rx interrupt */
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#define INT_COMMTx 3 /* Debug Comm Tx interrupt */
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#define INT_TIMERINT0_1 4 /* Timer 0 and 1 */
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#define INT_TIMERINT2_3 5 /* Timer 2 and 3 */
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#define INT_GPIOINT0 6 /* GPIO 0 */
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#define INT_GPIOINT1 7 /* GPIO 1 */
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#define INT_GPIOINT2 8 /* GPIO 2 */
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#define INT_GPIOINT3 9 /* GPIO 3 */
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#define INT_RTCINT 10 /* Real Time Clock */
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#define INT_SSPINT 11 /* Synchronous Serial Port */
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#define INT_UARTINT0 12 /* UART 0 on development chip */
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#define INT_UARTINT1 13 /* UART 1 on development chip */
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#define INT_UARTINT2 14 /* UART 2 on development chip */
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#define INT_SCIINT 15 /* Smart Card Interface */
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#define INT_CLCDINT 16 /* CLCD controller */
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#define INT_DMAINT 17 /* DMA controller */
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#define INT_PWRFAILINT 18 /* Power failure */
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#define INT_MBXINT 19 /* Graphics processor */
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#define INT_GNDINT 20 /* Reserved */
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/* External interrupt signals from logic tiles or secondary controller */
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#define INT_VICSOURCE21 21 /* Disk on Chip */
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#define INT_VICSOURCE22 22 /* MCI0A */
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#define INT_VICSOURCE23 23 /* MCI1A */
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#define INT_VICSOURCE24 24 /* AACI */
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#define INT_VICSOURCE25 25 /* Ethernet */
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#define INT_VICSOURCE26 26 /* USB */
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#define INT_VICSOURCE27 27 /* PCI 0 */
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#define INT_VICSOURCE28 28 /* PCI 1 */
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#define INT_VICSOURCE29 29 /* PCI 2 */
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#define INT_VICSOURCE30 30 /* PCI 3 */
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#define INT_VICSOURCE31 31 /* SIC source */
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/*
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* Interrupt bit positions
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*
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*/
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#define INTMASK_WDOGINT (1 << INT_WDOGINT)
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#define INTMASK_SOFTINT (1 << INT_SOFTINT)
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#define INTMASK_COMMRx (1 << INT_COMMRx)
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#define INTMASK_COMMTx (1 << INT_COMMTx)
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#define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1)
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#define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3)
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#define INTMASK_GPIOINT0 (1 << INT_GPIOINT0)
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#define INTMASK_GPIOINT1 (1 << INT_GPIOINT1)
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#define INTMASK_GPIOINT2 (1 << INT_GPIOINT2)
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#define INTMASK_GPIOINT3 (1 << INT_GPIOINT3)
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#define INTMASK_RTCINT (1 << INT_RTCINT)
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#define INTMASK_SSPINT (1 << INT_SSPINT)
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#define INTMASK_UARTINT0 (1 << INT_UARTINT0)
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#define INTMASK_UARTINT1 (1 << INT_UARTINT1)
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#define INTMASK_UARTINT2 (1 << INT_UARTINT2)
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#define INTMASK_SCIINT (1 << INT_SCIINT)
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#define INTMASK_CLCDINT (1 << INT_CLCDINT)
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#define INTMASK_DMAINT (1 << INT_DMAINT)
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#define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT)
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#define INTMASK_MBXINT (1 << INT_MBXINT)
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#define INTMASK_GNDINT (1 << INT_GNDINT)
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#define INTMASK_VICSOURCE21 (1 << INT_VICSOURCE21)
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#define INTMASK_VICSOURCE22 (1 << INT_VICSOURCE22)
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#define INTMASK_VICSOURCE23 (1 << INT_VICSOURCE23)
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#define INTMASK_VICSOURCE24 (1 << INT_VICSOURCE24)
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#define INTMASK_VICSOURCE25 (1 << INT_VICSOURCE25)
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#define INTMASK_VICSOURCE26 (1 << INT_VICSOURCE26)
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#define INTMASK_VICSOURCE27 (1 << INT_VICSOURCE27)
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#define INTMASK_VICSOURCE28 (1 << INT_VICSOURCE28)
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#define INTMASK_VICSOURCE29 (1 << INT_VICSOURCE29)
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#define INTMASK_VICSOURCE30 (1 << INT_VICSOURCE30)
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#define INTMASK_VICSOURCE31 (1 << INT_VICSOURCE31)
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#define VERSATILE_SC_VALID_INT 0x003FFFFF
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#define MAXIRQNUM 31
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#define MAXFIQNUM 31
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#define MAXSWINUM 31
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/* ------------------------------------------------------------------------
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* Interrupts - bit assignment (secondary)
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* ------------------------------------------------------------------------
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*/
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#define SIC_INT_MMCI0B 1 /* Multimedia Card 0B */
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#define SIC_INT_MMCI1B 2 /* Multimedia Card 1B */
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#define SIC_INT_KMI0 3 /* Keyboard/Mouse port 0 */
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#define SIC_INT_KMI1 4 /* Keyboard/Mouse port 1 */
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#define SIC_INT_SCI3 5 /* Smart Card interface */
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#define SIC_INT_UART3 6 /* UART 3 empty or data available */
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#define SIC_INT_CLCD 7 /* Character LCD */
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#define SIC_INT_TOUCH 8 /* Touchscreen */
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#define SIC_INT_KEYPAD 9 /* Key pressed on display keypad */
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/* 10:20 - reserved */
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#define SIC_INT_DoC 21 /* Disk on Chip memory controller */
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#define SIC_INT_MMCI0A 22 /* MMC 0A */
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#define SIC_INT_MMCI1A 23 /* MMC 1A */
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#define SIC_INT_AACI 24 /* Audio Codec */
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#define SIC_INT_ETH 25 /* Ethernet controller */
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#define SIC_INT_USB 26 /* USB controller */
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#define SIC_INT_PCI0 27
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#define SIC_INT_PCI1 28
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#define SIC_INT_PCI2 29
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#define SIC_INT_PCI3 30
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#define SIC_INTMASK_MMCI0B (1 << SIC_INT_MMCI0B)
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#define SIC_INTMASK_MMCI1B (1 << SIC_INT_MMCI1B)
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#define SIC_INTMASK_KMI0 (1 << SIC_INT_KMI0)
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#define SIC_INTMASK_KMI1 (1 << SIC_INT_KMI1)
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#define SIC_INTMASK_SCI3 (1 << SIC_INT_SCI3)
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#define SIC_INTMASK_UART3 (1 << SIC_INT_UART3)
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#define SIC_INTMASK_CLCD (1 << SIC_INT_CLCD)
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#define SIC_INTMASK_TOUCH (1 << SIC_INT_TOUCH)
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#define SIC_INTMASK_KEYPAD (1 << SIC_INT_KEYPAD)
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#define SIC_INTMASK_DoC (1 << SIC_INT_DoC)
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#define SIC_INTMASK_MMCI0A (1 << SIC_INT_MMCI0A)
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#define SIC_INTMASK_MMCI1A (1 << SIC_INT_MMCI1A)
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#define SIC_INTMASK_AACI (1 << SIC_INT_AACI)
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#define SIC_INTMASK_ETH (1 << SIC_INT_ETH)
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#define SIC_INTMASK_USB (1 << SIC_INT_USB)
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#define SIC_INTMASK_PCI0 (1 << SIC_INT_PCI0)
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#define SIC_INTMASK_PCI1 (1 << SIC_INT_PCI1)
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#define SIC_INTMASK_PCI2 (1 << SIC_INT_PCI2)
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#define SIC_INTMASK_PCI3 (1 << SIC_INT_PCI3)
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/*
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* Application Flash
|
|
*
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*/
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#define FLASH_BASE VERSATILE_FLASH_BASE
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#define FLASH_SIZE VERSATILE_FLASH_SIZE
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#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1)
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#define FLASH_BLOCK_SIZE SZ_128K
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|
|
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/*
|
|
* Boot Flash
|
|
*
|
|
*/
|
|
#define EPROM_BASE VERSATILE_BOOT_ROM_HI
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#define EPROM_SIZE VERSATILE_BOOT_ROM_SIZE
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#define EPROM_END (EPROM_BASE + EPROM_SIZE - 1)
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|
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/*
|
|
* Clean base - dummy
|
|
*
|
|
*/
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#define CLEAN_BASE EPROM_BASE
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|
|
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/*
|
|
* System controller bit assignment
|
|
*/
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#define VERSATILE_REFCLK 0
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#define VERSATILE_TIMCLK 1
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|
|
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#define VERSATILE_TIMER1_EnSel 15
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|
#define VERSATILE_TIMER2_EnSel 17
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|
#define VERSATILE_TIMER3_EnSel 19
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|
#define VERSATILE_TIMER4_EnSel 21
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|
|
|
|
|
#define MAX_TIMER 2
|
|
#define MAX_PERIOD 699050
|
|
#define TICKS_PER_uSEC 1
|
|
|
|
/*
|
|
* These are useconds NOT ticks.
|
|
*
|
|
*/
|
|
#define mSEC_1 1000
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|
#define mSEC_5 (mSEC_1 * 5)
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#define mSEC_10 (mSEC_1 * 10)
|
|
#define mSEC_25 (mSEC_1 * 25)
|
|
#define SEC_1 (mSEC_1 * 1000)
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|
|
|
#define VERSATILE_CSR_BASE 0x10000000
|
|
#define VERSATILE_CSR_SIZE 0x10000000
|
|
|
|
#ifdef CONFIG_MACH_VERSATILE_AB
|
|
/*
|
|
* IB2 Versatile/AB expansion board definitions
|
|
*/
|
|
#define VERSATILE_IB2_CAMERA_BANK VERSATILE_IB2_BASE
|
|
#define VERSATILE_IB2_KBD_DATAREG (VERSATILE_IB2_BASE + 0x01000000)
|
|
|
|
/* VICINTSOURCE27 */
|
|
#define VERSATILE_IB2_INT_BASE (VERSATILE_IB2_BASE + 0x02000000)
|
|
#define VERSATILE_IB2_IER (VERSATILE_IB2_INT_BASE + 0)
|
|
#define VERSATILE_IB2_ISR (VERSATILE_IB2_INT_BASE + 4)
|
|
|
|
#define VERSATILE_IB2_CTL_BASE (VERSATILE_IB2_BASE + 0x03000000)
|
|
#define VERSATILE_IB2_CTRL (VERSATILE_IB2_CTL_BASE + 0)
|
|
#define VERSATILE_IB2_STAT (VERSATILE_IB2_CTL_BASE + 4)
|
|
#endif
|
|
|
|
#endif
|
|
|
|
/* END */
|