mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 13:46:47 +07:00
8f8f484bf3
Add Tegra specific clocks, pll, pll_out, peripheral, frac_divider, super.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: alloc sizeof(*foo) not sizeof(struct foo), add comments re:
storing pointers to stack variables, make a timeout loop more idiomatic,
use _clk_pll_disable() not clk_disable_pll() from _program_pll() to
avoid redundant lock operations, unified tegra_clk_periph() and
tegra_clk_periph_nodiv(), unified tegra_clk_pll{,e}, rename all clock
registration functions so they don't have the same name as the clock
structs, return -EINVAL from clk_plle_enable when matching table rate
not found, pass ops to _tegra_clk_register_pll rather than a bool.]
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
124 lines
3.1 KiB
C
124 lines
3.1 KiB
C
/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/clk-provider.h>
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#include <linux/clk.h>
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#include "clk.h"
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#define pll_out_enb(p) (BIT(p->enb_bit_idx))
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#define pll_out_rst(p) (BIT(p->rst_bit_idx))
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static int clk_pll_out_is_enabled(struct clk_hw *hw)
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{
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struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
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u32 val = readl_relaxed(pll_out->reg);
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int state;
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state = (val & pll_out_enb(pll_out)) ? 1 : 0;
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if (!(val & (pll_out_rst(pll_out))))
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state = 0;
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return state;
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}
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static int clk_pll_out_enable(struct clk_hw *hw)
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{
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struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
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unsigned long flags = 0;
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u32 val;
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if (pll_out->lock)
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spin_lock_irqsave(pll_out->lock, flags);
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val = readl_relaxed(pll_out->reg);
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val |= (pll_out_enb(pll_out) | pll_out_rst(pll_out));
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writel_relaxed(val, pll_out->reg);
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udelay(2);
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if (pll_out->lock)
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spin_unlock_irqrestore(pll_out->lock, flags);
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return 0;
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}
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static void clk_pll_out_disable(struct clk_hw *hw)
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{
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struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
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unsigned long flags = 0;
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u32 val;
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if (pll_out->lock)
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spin_lock_irqsave(pll_out->lock, flags);
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val = readl_relaxed(pll_out->reg);
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val &= ~(pll_out_enb(pll_out) | pll_out_rst(pll_out));
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writel_relaxed(val, pll_out->reg);
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udelay(2);
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if (pll_out->lock)
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spin_unlock_irqrestore(pll_out->lock, flags);
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}
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const struct clk_ops tegra_clk_pll_out_ops = {
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.is_enabled = clk_pll_out_is_enabled,
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.enable = clk_pll_out_enable,
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.disable = clk_pll_out_disable,
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};
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struct clk *tegra_clk_register_pll_out(const char *name,
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const char *parent_name, void __iomem *reg, u8 enb_bit_idx,
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u8 rst_bit_idx, unsigned long flags, u8 pll_out_flags,
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spinlock_t *lock)
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{
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struct tegra_clk_pll_out *pll_out;
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struct clk *clk;
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struct clk_init_data init;
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pll_out = kzalloc(sizeof(*pll_out), GFP_KERNEL);
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if (!pll_out)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &tegra_clk_pll_out_ops;
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init.parent_names = (parent_name ? &parent_name : NULL);
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init.num_parents = (parent_name ? 1 : 0);
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init.flags = flags;
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pll_out->reg = reg;
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pll_out->enb_bit_idx = enb_bit_idx;
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pll_out->rst_bit_idx = rst_bit_idx;
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pll_out->flags = pll_out_flags;
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pll_out->lock = lock;
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/* Data in .init is copied by clk_register(), so stack variable OK */
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pll_out->hw.init = &init;
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clk = clk_register(NULL, &pll_out->hw);
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if (IS_ERR(clk))
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kfree(pll_out);
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return clk;
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}
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