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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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044ac37d12
So far, we've implemented the new world switch with a completely different namespace, so that we could have both implementation compiled in. Let's take things one step further by adding weak aliases that have the same names as the original implementation. The weak attributes allows the new implementation to be overriden by the old one, and everything still work. At a later point, we'll be able to simply drop the old code, and everything will hopefully keep working, thanks to the aliases we have just added. This also saves us repainting all the callers. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
83 lines
2.1 KiB
C
83 lines
2.1 KiB
C
/*
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* Copyright (C) 2015 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hyp.h"
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void __hyp_text __tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)
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{
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dsb(ishst);
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/* Switch to requested VMID */
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kvm = kern_hyp_va(kvm);
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write_sysreg(kvm->arch.vttbr, vttbr_el2);
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isb();
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/*
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* We could do so much better if we had the VA as well.
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* Instead, we invalidate Stage-2 for this IPA, and the
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* whole of Stage-1. Weep...
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*/
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ipa >>= 12;
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asm volatile("tlbi ipas2e1is, %0" : : "r" (ipa));
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/*
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* We have to ensure completion of the invalidation at Stage-2,
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* since a table walk on another CPU could refill a TLB with a
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* complete (S1 + S2) walk based on the old Stage-2 mapping if
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* the Stage-1 invalidation happened first.
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*/
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dsb(ish);
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asm volatile("tlbi vmalle1is" : : );
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dsb(ish);
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isb();
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write_sysreg(0, vttbr_el2);
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}
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__alias(__tlb_flush_vmid_ipa)
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void __weak __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
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void __hyp_text __tlb_flush_vmid(struct kvm *kvm)
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{
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dsb(ishst);
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/* Switch to requested VMID */
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kvm = kern_hyp_va(kvm);
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write_sysreg(kvm->arch.vttbr, vttbr_el2);
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isb();
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asm volatile("tlbi vmalls12e1is" : : );
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dsb(ish);
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isb();
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write_sysreg(0, vttbr_el2);
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}
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__alias(__tlb_flush_vmid)
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void __weak __kvm_tlb_flush_vmid(struct kvm *kvm);
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void __hyp_text __tlb_flush_vm_context(void)
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{
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dsb(ishst);
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asm volatile("tlbi alle1is \n"
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"ic ialluis ": : );
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dsb(ish);
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}
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__alias(__tlb_flush_vm_context)
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void __weak __kvm_flush_vm_context(void);
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