Dmitry Osipenko 9fddbe9495 clk: tegra30: Use 300MHz for video decoder by default ... [ Upstream commit 56bb7c28ad00e7bcfc851c4e183c42d148d3ad4e ] The 600MHz is a too high clock rate for some SoC versions for the video decoder hardware and this may cause stability issues. Use 300MHz for the video decoder by default, which is supported by all hardware versions. Fixes: ed1a2459e2 ("clk: tegra: Add Tegra20/30 EMC clock implementation") Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sasha Levin <sashal@kernel.org>		2021-07-14 16:56:19 +02:00
..
clk-audio-sync.c
clk-bpmp.c
clk-dfll.c	clk: tegra: Do not return 0 on failure	2020-12-30 11:54:26 +01:00
clk-dfll.h
clk-divider.c
clk-id.h	clk: tegra: Fix duplicated SE clock entry	2020-12-30 11:53:49 +01:00
clk-periph-fixed.c
clk-periph-gate.c
clk-periph.c
clk-pll-out.c
clk-pll.c	clk: tegra: Always program PLL_E when enabled	2020-09-21 14:09:09 +02:00
clk-sdmmc-mux.c
clk-super.c
clk-tegra20-emc.c
clk-tegra20.c
clk-tegra30.c	clk: tegra30: Use 300MHz for video decoder by default	2021-07-14 16:56:19 +02:00
clk-tegra114.c
clk-tegra124-dfll-fcpu.c
clk-tegra124-emc.c
clk-tegra124.c
clk-tegra210-emc.c	This pull request contains zero diff to the core framework. It is a collection	2020-10-22 12:53:28 -07:00
clk-tegra210.c
clk-tegra-audio.c
clk-tegra-fixed.c
clk-tegra-periph.c	clk: tegra: Fix duplicated SE clock entry	2020-12-30 11:53:49 +01:00
clk-tegra-super-cclk.c
clk-tegra-super-gen4.c
clk-utils.c
clk.c
clk.h
cvb.c
cvb.h
Kconfig
Makefile