mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-18 00:26:47 +07:00
033b7a230c
This will get rid of the following error: [ 74.730271] WARNING: CPU: 4 PID: 0 at drivers/gpu/drm/drm_vblank.c:614 drm_calc_vbltimestamp_from_scanoutpos+0x13e/0x2f0 [ 74.730311] Modules linked in: vgem snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic i915 x86_pkg_temp_thermal intel_powerclamp coretemp snd_hda_intel crct10dif_pclmul snd_hda_codec crc32_pclmul snd_hwdep broadcom ghash_clmulni_intel snd_hda_core bcm_phy_lib snd_pcm tg3 lpc_ich mei_me mei prime_numbers [ 74.730353] CPU: 4 PID: 0 Comm: swapper/4 Tainted: G U 4.16.0-rc2-CI-CI_DRM_3822+ #1 [ 74.730355] Hardware name: Dell Inc. XPS 8300 /0Y2MRG, BIOS A06 10/17/2011 [ 74.730359] RIP: 0010:drm_calc_vbltimestamp_from_scanoutpos+0x13e/0x2f0 [ 74.730361] RSP: 0018:ffff88022fb03d10 EFLAGS: 00010086 [ 74.730365] RAX: ffffffffa0291d20 RBX: ffff88021a180000 RCX: 0000000000000001 [ 74.730367] RDX: ffffffff820e7db8 RSI: 0000000000000001 RDI: ffffffff82068cea [ 74.730369] RBP: ffff88022fb03d70 R08: 0000000000000000 R09: ffffffff815d26d0 [ 74.730371] R10: 0000000000000000 R11: ffffffffa0161ca0 R12: 0000000000000001 [ 74.730373] R13: ffff880212448008 R14: ffff880212448330 R15: 0000000000000000 [ 74.730376] FS: 0000000000000000(0000) GS:ffff88022fb00000(0000) knlGS:0000000000000000 [ 74.730378] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 74.730380] CR2: 000055edcbec9000 CR3: 0000000002210001 CR4: 00000000000606e0 [ 74.730382] Call Trace: [ 74.730385] <IRQ> [ 74.730397] drm_get_last_vbltimestamp+0x36/0x50 [ 74.730401] drm_update_vblank_count+0x64/0x240 [ 74.730409] drm_crtc_accurate_vblank_count+0x41/0x90 [ 74.730453] display_pipe_crc_irq_handler+0x176/0x220 [i915] [ 74.730497] i9xx_pipe_crc_irq_handler+0xfe/0x150 [i915] [ 74.730537] ironlake_irq_handler+0x618/0xa30 [i915] [ 74.730548] __handle_irq_event_percpu+0x3c/0x340 [ 74.730556] handle_irq_event_percpu+0x1b/0x50 [ 74.730561] handle_irq_event+0x2f/0x50 [ 74.730566] handle_edge_irq+0xe4/0x1b0 [ 74.730572] handle_irq+0x11/0x20 [ 74.730576] do_IRQ+0x5e/0x120 [ 74.730584] common_interrupt+0x84/0x84 [ 74.730586] </IRQ> [ 74.730591] RIP: 0010:cpuidle_enter_state+0xaa/0x350 [ 74.730593] RSP: 0018:ffffc9000008beb8 EFLAGS: 00000212 ORIG_RAX: ffffffffffffffde [ 74.730597] RAX: ffff880226b80040 RBX: 000000000031fc3e RCX: 0000000000000001 [ 74.730599] RDX: 0000000000000000 RSI: ffffffff8210fb59 RDI: ffffffff820c02e7 [ 74.730601] RBP: 0000000000000004 R08: 00000000000040af R09: 0000000000000018 [ 74.730603] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000004 [ 74.730606] R13: ffffe8ffffd00430 R14: 0000001166120bf4 R15: ffffffff82294460 [ 74.730621] ? cpuidle_enter_state+0xa6/0x350 [ 74.730629] do_idle+0x188/0x1d0 [ 74.730636] cpu_startup_entry+0x14/0x20 [ 74.730641] start_secondary+0x129/0x160 [ 74.730646] secondary_startup_64+0xa5/0xb0 [ 74.730660] Code: e1 48 c7 c2 b8 7d 0e 82 be 01 00 00 00 48 c7 c7 ea 8c 06 82 e8 64 ec ff ff 48 8b 83 c8 07 00 00 48 83 78 28 00 0f 84 e2 fe ff ff <0f> 0b 45 31 ed e9 db fe ff ff 41 b8 d3 4d 62 10 89 c8 6a 03 41 [ 74.730754] ---[ end trace 14b1345705b68565 ]--- Changes since v1: - Don't try to apply CRC workaround when enabling pipe, it should already be enabled. Changes since v2: - Make crc functions for !DEBUGFS case inline. - Pass intel_crtc to crc functions. - Add comments to callsites. Changes since v3: - Cache selected source to pipe_crc->source. - Set pipe_crc->skipped to MIN_INT during disable to close a race condition. Changes since v4: - Handle fallout from setting pipe_crc->source in irq handler. Cc: Marta Löfstedt <marta.lofstedt@intel.com> Reported-by: Marta Löfstedt <marta.lofstedt@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105185 Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180308120202.52446-1-maarten.lankhorst@linux.intel.com Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
1001 lines
24 KiB
C
1001 lines
24 KiB
C
/*
|
|
* Copyright © 2013 Intel Corporation
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
* to deal in the Software without restriction, including without limitation
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice (including the next
|
|
* paragraph) shall be included in all copies or substantial portions of the
|
|
* Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
|
* IN THE SOFTWARE.
|
|
*
|
|
* Author: Damien Lespiau <damien.lespiau@intel.com>
|
|
*
|
|
*/
|
|
|
|
#include <linux/seq_file.h>
|
|
#include <linux/circ_buf.h>
|
|
#include <linux/ctype.h>
|
|
#include <linux/debugfs.h>
|
|
#include "intel_drv.h"
|
|
|
|
struct pipe_crc_info {
|
|
const char *name;
|
|
struct drm_i915_private *dev_priv;
|
|
enum pipe pipe;
|
|
};
|
|
|
|
static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
|
|
{
|
|
struct pipe_crc_info *info = inode->i_private;
|
|
struct drm_i915_private *dev_priv = info->dev_priv;
|
|
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
|
|
|
|
if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes)
|
|
return -ENODEV;
|
|
|
|
spin_lock_irq(&pipe_crc->lock);
|
|
|
|
if (pipe_crc->opened) {
|
|
spin_unlock_irq(&pipe_crc->lock);
|
|
return -EBUSY; /* already open */
|
|
}
|
|
|
|
pipe_crc->opened = true;
|
|
filep->private_data = inode->i_private;
|
|
|
|
spin_unlock_irq(&pipe_crc->lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
|
|
{
|
|
struct pipe_crc_info *info = inode->i_private;
|
|
struct drm_i915_private *dev_priv = info->dev_priv;
|
|
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
|
|
|
|
spin_lock_irq(&pipe_crc->lock);
|
|
pipe_crc->opened = false;
|
|
spin_unlock_irq(&pipe_crc->lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* (6 fields, 8 chars each, space separated (5) + '\n') */
|
|
#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
|
|
/* account for \'0' */
|
|
#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
|
|
|
|
static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
|
|
{
|
|
lockdep_assert_held(&pipe_crc->lock);
|
|
return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
|
|
INTEL_PIPE_CRC_ENTRIES_NR);
|
|
}
|
|
|
|
static ssize_t
|
|
i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
|
|
loff_t *pos)
|
|
{
|
|
struct pipe_crc_info *info = filep->private_data;
|
|
struct drm_i915_private *dev_priv = info->dev_priv;
|
|
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
|
|
char buf[PIPE_CRC_BUFFER_LEN];
|
|
int n_entries;
|
|
ssize_t bytes_read;
|
|
|
|
/*
|
|
* Don't allow user space to provide buffers not big enough to hold
|
|
* a line of data.
|
|
*/
|
|
if (count < PIPE_CRC_LINE_LEN)
|
|
return -EINVAL;
|
|
|
|
if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
|
|
return 0;
|
|
|
|
/* nothing to read */
|
|
spin_lock_irq(&pipe_crc->lock);
|
|
while (pipe_crc_data_count(pipe_crc) == 0) {
|
|
int ret;
|
|
|
|
if (filep->f_flags & O_NONBLOCK) {
|
|
spin_unlock_irq(&pipe_crc->lock);
|
|
return -EAGAIN;
|
|
}
|
|
|
|
ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
|
|
pipe_crc_data_count(pipe_crc), pipe_crc->lock);
|
|
if (ret) {
|
|
spin_unlock_irq(&pipe_crc->lock);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
/* We now have one or more entries to read */
|
|
n_entries = count / PIPE_CRC_LINE_LEN;
|
|
|
|
bytes_read = 0;
|
|
while (n_entries > 0) {
|
|
struct intel_pipe_crc_entry *entry =
|
|
&pipe_crc->entries[pipe_crc->tail];
|
|
|
|
if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
|
|
INTEL_PIPE_CRC_ENTRIES_NR) < 1)
|
|
break;
|
|
|
|
BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
|
|
pipe_crc->tail = (pipe_crc->tail + 1) &
|
|
(INTEL_PIPE_CRC_ENTRIES_NR - 1);
|
|
|
|
bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
|
|
"%8u %8x %8x %8x %8x %8x\n",
|
|
entry->frame, entry->crc[0],
|
|
entry->crc[1], entry->crc[2],
|
|
entry->crc[3], entry->crc[4]);
|
|
|
|
spin_unlock_irq(&pipe_crc->lock);
|
|
|
|
if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN))
|
|
return -EFAULT;
|
|
|
|
user_buf += PIPE_CRC_LINE_LEN;
|
|
n_entries--;
|
|
|
|
spin_lock_irq(&pipe_crc->lock);
|
|
}
|
|
|
|
spin_unlock_irq(&pipe_crc->lock);
|
|
|
|
return bytes_read;
|
|
}
|
|
|
|
static const struct file_operations i915_pipe_crc_fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = i915_pipe_crc_open,
|
|
.read = i915_pipe_crc_read,
|
|
.release = i915_pipe_crc_release,
|
|
};
|
|
|
|
static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
|
|
{
|
|
.name = "i915_pipe_A_crc",
|
|
.pipe = PIPE_A,
|
|
},
|
|
{
|
|
.name = "i915_pipe_B_crc",
|
|
.pipe = PIPE_B,
|
|
},
|
|
{
|
|
.name = "i915_pipe_C_crc",
|
|
.pipe = PIPE_C,
|
|
},
|
|
};
|
|
|
|
static const char * const pipe_crc_sources[] = {
|
|
"none",
|
|
"plane1",
|
|
"plane2",
|
|
"pf",
|
|
"pipe",
|
|
"TV",
|
|
"DP-B",
|
|
"DP-C",
|
|
"DP-D",
|
|
"auto",
|
|
};
|
|
|
|
static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
|
|
{
|
|
BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
|
|
return pipe_crc_sources[source];
|
|
}
|
|
|
|
static int display_crc_ctl_show(struct seq_file *m, void *data)
|
|
{
|
|
struct drm_i915_private *dev_priv = m->private;
|
|
enum pipe pipe;
|
|
|
|
for_each_pipe(dev_priv, pipe)
|
|
seq_printf(m, "%c %s\n", pipe_name(pipe),
|
|
pipe_crc_source_name(dev_priv->pipe_crc[pipe].source));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int display_crc_ctl_open(struct inode *inode, struct file *file)
|
|
{
|
|
return single_open(file, display_crc_ctl_show, inode->i_private);
|
|
}
|
|
|
|
static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
|
|
uint32_t *val)
|
|
{
|
|
if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
|
|
*source = INTEL_PIPE_CRC_SOURCE_PIPE;
|
|
|
|
switch (*source) {
|
|
case INTEL_PIPE_CRC_SOURCE_PIPE:
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
|
|
break;
|
|
case INTEL_PIPE_CRC_SOURCE_NONE:
|
|
*val = 0;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
|
|
enum pipe pipe,
|
|
enum intel_pipe_crc_source *source)
|
|
{
|
|
struct drm_device *dev = &dev_priv->drm;
|
|
struct intel_encoder *encoder;
|
|
struct intel_crtc *crtc;
|
|
struct intel_digital_port *dig_port;
|
|
int ret = 0;
|
|
|
|
*source = INTEL_PIPE_CRC_SOURCE_PIPE;
|
|
|
|
drm_modeset_lock_all(dev);
|
|
for_each_intel_encoder(dev, encoder) {
|
|
if (!encoder->base.crtc)
|
|
continue;
|
|
|
|
crtc = to_intel_crtc(encoder->base.crtc);
|
|
|
|
if (crtc->pipe != pipe)
|
|
continue;
|
|
|
|
switch (encoder->type) {
|
|
case INTEL_OUTPUT_TVOUT:
|
|
*source = INTEL_PIPE_CRC_SOURCE_TV;
|
|
break;
|
|
case INTEL_OUTPUT_DP:
|
|
case INTEL_OUTPUT_EDP:
|
|
dig_port = enc_to_dig_port(&encoder->base);
|
|
switch (dig_port->base.port) {
|
|
case PORT_B:
|
|
*source = INTEL_PIPE_CRC_SOURCE_DP_B;
|
|
break;
|
|
case PORT_C:
|
|
*source = INTEL_PIPE_CRC_SOURCE_DP_C;
|
|
break;
|
|
case PORT_D:
|
|
*source = INTEL_PIPE_CRC_SOURCE_DP_D;
|
|
break;
|
|
default:
|
|
WARN(1, "nonexisting DP port %c\n",
|
|
port_name(dig_port->base.port));
|
|
break;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
drm_modeset_unlock_all(dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
|
|
enum pipe pipe,
|
|
enum intel_pipe_crc_source *source,
|
|
uint32_t *val)
|
|
{
|
|
bool need_stable_symbols = false;
|
|
|
|
if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
|
|
int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
switch (*source) {
|
|
case INTEL_PIPE_CRC_SOURCE_PIPE:
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
|
|
break;
|
|
case INTEL_PIPE_CRC_SOURCE_DP_B:
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
|
|
need_stable_symbols = true;
|
|
break;
|
|
case INTEL_PIPE_CRC_SOURCE_DP_C:
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
|
|
need_stable_symbols = true;
|
|
break;
|
|
case INTEL_PIPE_CRC_SOURCE_DP_D:
|
|
if (!IS_CHERRYVIEW(dev_priv))
|
|
return -EINVAL;
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
|
|
need_stable_symbols = true;
|
|
break;
|
|
case INTEL_PIPE_CRC_SOURCE_NONE:
|
|
*val = 0;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* When the pipe CRC tap point is after the transcoders we need
|
|
* to tweak symbol-level features to produce a deterministic series of
|
|
* symbols for a given frame. We need to reset those features only once
|
|
* a frame (instead of every nth symbol):
|
|
* - DC-balance: used to ensure a better clock recovery from the data
|
|
* link (SDVO)
|
|
* - DisplayPort scrambling: used for EMI reduction
|
|
*/
|
|
if (need_stable_symbols) {
|
|
uint32_t tmp = I915_READ(PORT_DFT2_G4X);
|
|
|
|
tmp |= DC_BALANCE_RESET_VLV;
|
|
switch (pipe) {
|
|
case PIPE_A:
|
|
tmp |= PIPE_A_SCRAMBLE_RESET;
|
|
break;
|
|
case PIPE_B:
|
|
tmp |= PIPE_B_SCRAMBLE_RESET;
|
|
break;
|
|
case PIPE_C:
|
|
tmp |= PIPE_C_SCRAMBLE_RESET;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
I915_WRITE(PORT_DFT2_G4X, tmp);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
|
|
enum pipe pipe,
|
|
enum intel_pipe_crc_source *source,
|
|
uint32_t *val)
|
|
{
|
|
bool need_stable_symbols = false;
|
|
|
|
if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
|
|
int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
switch (*source) {
|
|
case INTEL_PIPE_CRC_SOURCE_PIPE:
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
|
|
break;
|
|
case INTEL_PIPE_CRC_SOURCE_TV:
|
|
if (!SUPPORTS_TV(dev_priv))
|
|
return -EINVAL;
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
|
|
break;
|
|
case INTEL_PIPE_CRC_SOURCE_DP_B:
|
|
if (!IS_G4X(dev_priv))
|
|
return -EINVAL;
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
|
|
need_stable_symbols = true;
|
|
break;
|
|
case INTEL_PIPE_CRC_SOURCE_DP_C:
|
|
if (!IS_G4X(dev_priv))
|
|
return -EINVAL;
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
|
|
need_stable_symbols = true;
|
|
break;
|
|
case INTEL_PIPE_CRC_SOURCE_DP_D:
|
|
if (!IS_G4X(dev_priv))
|
|
return -EINVAL;
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
|
|
need_stable_symbols = true;
|
|
break;
|
|
case INTEL_PIPE_CRC_SOURCE_NONE:
|
|
*val = 0;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* When the pipe CRC tap point is after the transcoders we need
|
|
* to tweak symbol-level features to produce a deterministic series of
|
|
* symbols for a given frame. We need to reset those features only once
|
|
* a frame (instead of every nth symbol):
|
|
* - DC-balance: used to ensure a better clock recovery from the data
|
|
* link (SDVO)
|
|
* - DisplayPort scrambling: used for EMI reduction
|
|
*/
|
|
if (need_stable_symbols) {
|
|
uint32_t tmp = I915_READ(PORT_DFT2_G4X);
|
|
|
|
WARN_ON(!IS_G4X(dev_priv));
|
|
|
|
I915_WRITE(PORT_DFT_I9XX,
|
|
I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
|
|
|
|
if (pipe == PIPE_A)
|
|
tmp |= PIPE_A_SCRAMBLE_RESET;
|
|
else
|
|
tmp |= PIPE_B_SCRAMBLE_RESET;
|
|
|
|
I915_WRITE(PORT_DFT2_G4X, tmp);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
|
|
enum pipe pipe)
|
|
{
|
|
uint32_t tmp = I915_READ(PORT_DFT2_G4X);
|
|
|
|
switch (pipe) {
|
|
case PIPE_A:
|
|
tmp &= ~PIPE_A_SCRAMBLE_RESET;
|
|
break;
|
|
case PIPE_B:
|
|
tmp &= ~PIPE_B_SCRAMBLE_RESET;
|
|
break;
|
|
case PIPE_C:
|
|
tmp &= ~PIPE_C_SCRAMBLE_RESET;
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
|
|
tmp &= ~DC_BALANCE_RESET_VLV;
|
|
I915_WRITE(PORT_DFT2_G4X, tmp);
|
|
|
|
}
|
|
|
|
static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
|
|
enum pipe pipe)
|
|
{
|
|
uint32_t tmp = I915_READ(PORT_DFT2_G4X);
|
|
|
|
if (pipe == PIPE_A)
|
|
tmp &= ~PIPE_A_SCRAMBLE_RESET;
|
|
else
|
|
tmp &= ~PIPE_B_SCRAMBLE_RESET;
|
|
I915_WRITE(PORT_DFT2_G4X, tmp);
|
|
|
|
if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
|
|
I915_WRITE(PORT_DFT_I9XX,
|
|
I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
|
|
}
|
|
}
|
|
|
|
static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
|
|
uint32_t *val)
|
|
{
|
|
if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
|
|
*source = INTEL_PIPE_CRC_SOURCE_PIPE;
|
|
|
|
switch (*source) {
|
|
case INTEL_PIPE_CRC_SOURCE_PLANE1:
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
|
|
break;
|
|
case INTEL_PIPE_CRC_SOURCE_PLANE2:
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
|
|
break;
|
|
case INTEL_PIPE_CRC_SOURCE_PIPE:
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
|
|
break;
|
|
case INTEL_PIPE_CRC_SOURCE_NONE:
|
|
*val = 0;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void hsw_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
|
|
bool enable)
|
|
{
|
|
struct drm_device *dev = &dev_priv->drm;
|
|
struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
|
|
struct intel_crtc_state *pipe_config;
|
|
struct drm_atomic_state *state;
|
|
struct drm_modeset_acquire_ctx ctx;
|
|
int ret = 0;
|
|
|
|
drm_modeset_acquire_init(&ctx, 0);
|
|
|
|
state = drm_atomic_state_alloc(dev);
|
|
if (!state) {
|
|
ret = -ENOMEM;
|
|
goto unlock;
|
|
}
|
|
|
|
state->acquire_ctx = &ctx;
|
|
|
|
retry:
|
|
pipe_config = intel_atomic_get_crtc_state(state, crtc);
|
|
if (IS_ERR(pipe_config)) {
|
|
ret = PTR_ERR(pipe_config);
|
|
goto put_state;
|
|
}
|
|
|
|
if (HAS_IPS(dev_priv)) {
|
|
/*
|
|
* When IPS gets enabled, the pipe CRC changes. Since IPS gets
|
|
* enabled and disabled dynamically based on package C states,
|
|
* user space can't make reliable use of the CRCs, so let's just
|
|
* completely disable it.
|
|
*/
|
|
pipe_config->ips_force_disable = enable;
|
|
}
|
|
|
|
if (IS_HASWELL(dev_priv)) {
|
|
pipe_config->pch_pfit.force_thru = enable;
|
|
if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
|
|
pipe_config->pch_pfit.enabled != enable)
|
|
pipe_config->base.connectors_changed = true;
|
|
}
|
|
|
|
ret = drm_atomic_commit(state);
|
|
|
|
put_state:
|
|
if (ret == -EDEADLK) {
|
|
drm_atomic_state_clear(state);
|
|
drm_modeset_backoff(&ctx);
|
|
goto retry;
|
|
}
|
|
|
|
drm_atomic_state_put(state);
|
|
unlock:
|
|
WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
|
|
drm_modeset_drop_locks(&ctx);
|
|
drm_modeset_acquire_fini(&ctx);
|
|
}
|
|
|
|
static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
|
|
enum pipe pipe,
|
|
enum intel_pipe_crc_source *source,
|
|
uint32_t *val,
|
|
bool set_wa)
|
|
{
|
|
if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
|
|
*source = INTEL_PIPE_CRC_SOURCE_PF;
|
|
|
|
switch (*source) {
|
|
case INTEL_PIPE_CRC_SOURCE_PLANE1:
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
|
|
break;
|
|
case INTEL_PIPE_CRC_SOURCE_PLANE2:
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
|
|
break;
|
|
case INTEL_PIPE_CRC_SOURCE_PF:
|
|
if (set_wa && (IS_HASWELL(dev_priv) ||
|
|
IS_BROADWELL(dev_priv)) && pipe == PIPE_A)
|
|
hsw_pipe_A_crc_wa(dev_priv, true);
|
|
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
|
|
break;
|
|
case INTEL_PIPE_CRC_SOURCE_NONE:
|
|
*val = 0;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
|
|
enum pipe pipe,
|
|
enum intel_pipe_crc_source *source, u32 *val,
|
|
bool set_wa)
|
|
{
|
|
if (IS_GEN2(dev_priv))
|
|
return i8xx_pipe_crc_ctl_reg(source, val);
|
|
else if (INTEL_GEN(dev_priv) < 5)
|
|
return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
|
|
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
|
|
return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
|
|
else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
|
|
return ilk_pipe_crc_ctl_reg(source, val);
|
|
else
|
|
return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val, set_wa);
|
|
}
|
|
|
|
static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
|
|
enum pipe pipe,
|
|
enum intel_pipe_crc_source source)
|
|
{
|
|
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
|
|
enum intel_display_power_domain power_domain;
|
|
u32 val = 0; /* shut up gcc */
|
|
int ret;
|
|
|
|
if (pipe_crc->source == source)
|
|
return 0;
|
|
|
|
/* forbid changing the source without going back to 'none' */
|
|
if (pipe_crc->source && source)
|
|
return -EINVAL;
|
|
|
|
power_domain = POWER_DOMAIN_PIPE(pipe);
|
|
if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
|
|
DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
|
|
return -EIO;
|
|
}
|
|
|
|
ret = get_new_crc_ctl_reg(dev_priv, pipe, &source, &val, true);
|
|
if (ret != 0)
|
|
goto out;
|
|
|
|
/* none -> real source transition */
|
|
if (source) {
|
|
struct intel_pipe_crc_entry *entries;
|
|
|
|
DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
|
|
pipe_name(pipe), pipe_crc_source_name(source));
|
|
|
|
entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
|
|
sizeof(pipe_crc->entries[0]),
|
|
GFP_KERNEL);
|
|
if (!entries) {
|
|
ret = -ENOMEM;
|
|
goto out;
|
|
}
|
|
|
|
spin_lock_irq(&pipe_crc->lock);
|
|
kfree(pipe_crc->entries);
|
|
pipe_crc->entries = entries;
|
|
pipe_crc->head = 0;
|
|
pipe_crc->tail = 0;
|
|
spin_unlock_irq(&pipe_crc->lock);
|
|
}
|
|
|
|
pipe_crc->source = source;
|
|
|
|
I915_WRITE(PIPE_CRC_CTL(pipe), val);
|
|
POSTING_READ(PIPE_CRC_CTL(pipe));
|
|
|
|
/* real source -> none transition */
|
|
if (!source) {
|
|
struct intel_pipe_crc_entry *entries;
|
|
struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
|
|
pipe);
|
|
|
|
DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
|
|
pipe_name(pipe));
|
|
|
|
drm_modeset_lock(&crtc->base.mutex, NULL);
|
|
if (crtc->base.state->active)
|
|
intel_wait_for_vblank(dev_priv, pipe);
|
|
drm_modeset_unlock(&crtc->base.mutex);
|
|
|
|
spin_lock_irq(&pipe_crc->lock);
|
|
entries = pipe_crc->entries;
|
|
pipe_crc->entries = NULL;
|
|
pipe_crc->head = 0;
|
|
pipe_crc->tail = 0;
|
|
spin_unlock_irq(&pipe_crc->lock);
|
|
|
|
kfree(entries);
|
|
|
|
if (IS_G4X(dev_priv))
|
|
g4x_undo_pipe_scramble_reset(dev_priv, pipe);
|
|
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
|
|
vlv_undo_pipe_scramble_reset(dev_priv, pipe);
|
|
else if ((IS_HASWELL(dev_priv) ||
|
|
IS_BROADWELL(dev_priv)) && pipe == PIPE_A)
|
|
hsw_pipe_A_crc_wa(dev_priv, false);
|
|
}
|
|
|
|
ret = 0;
|
|
|
|
out:
|
|
intel_display_power_put(dev_priv, power_domain);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Parse pipe CRC command strings:
|
|
* command: wsp* object wsp+ name wsp+ source wsp*
|
|
* object: 'pipe'
|
|
* name: (A | B | C)
|
|
* source: (none | plane1 | plane2 | pf)
|
|
* wsp: (#0x20 | #0x9 | #0xA)+
|
|
*
|
|
* eg.:
|
|
* "pipe A plane1" -> Start CRC computations on plane1 of pipe A
|
|
* "pipe A none" -> Stop CRC
|
|
*/
|
|
static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
|
|
{
|
|
int n_words = 0;
|
|
|
|
while (*buf) {
|
|
char *end;
|
|
|
|
/* skip leading white space */
|
|
buf = skip_spaces(buf);
|
|
if (!*buf)
|
|
break; /* end of buffer */
|
|
|
|
/* find end of word */
|
|
for (end = buf; *end && !isspace(*end); end++)
|
|
;
|
|
|
|
if (n_words == max_words) {
|
|
DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
|
|
max_words);
|
|
return -EINVAL; /* ran out of words[] before bytes */
|
|
}
|
|
|
|
if (*end)
|
|
*end++ = '\0';
|
|
words[n_words++] = buf;
|
|
buf = end;
|
|
}
|
|
|
|
return n_words;
|
|
}
|
|
|
|
enum intel_pipe_crc_object {
|
|
PIPE_CRC_OBJECT_PIPE,
|
|
};
|
|
|
|
static const char * const pipe_crc_objects[] = {
|
|
"pipe",
|
|
};
|
|
|
|
static int
|
|
display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
|
|
if (!strcmp(buf, pipe_crc_objects[i])) {
|
|
*o = i;
|
|
return 0;
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int display_crc_ctl_parse_pipe(struct drm_i915_private *dev_priv,
|
|
const char *buf, enum pipe *pipe)
|
|
{
|
|
const char name = buf[0];
|
|
|
|
if (name < 'A' || name >= pipe_name(INTEL_INFO(dev_priv)->num_pipes))
|
|
return -EINVAL;
|
|
|
|
*pipe = name - 'A';
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
|
|
{
|
|
int i;
|
|
|
|
if (!buf) {
|
|
*s = INTEL_PIPE_CRC_SOURCE_NONE;
|
|
return 0;
|
|
}
|
|
|
|
for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
|
|
if (!strcmp(buf, pipe_crc_sources[i])) {
|
|
*s = i;
|
|
return 0;
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
|
|
char *buf, size_t len)
|
|
{
|
|
#define N_WORDS 3
|
|
int n_words;
|
|
char *words[N_WORDS];
|
|
enum pipe pipe;
|
|
enum intel_pipe_crc_object object;
|
|
enum intel_pipe_crc_source source;
|
|
|
|
n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
|
|
if (n_words != N_WORDS) {
|
|
DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
|
|
N_WORDS);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (display_crc_ctl_parse_object(words[0], &object) < 0) {
|
|
DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (display_crc_ctl_parse_pipe(dev_priv, words[1], &pipe) < 0) {
|
|
DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (display_crc_ctl_parse_source(words[2], &source) < 0) {
|
|
DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return pipe_crc_set_source(dev_priv, pipe, source);
|
|
}
|
|
|
|
static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
|
|
size_t len, loff_t *offp)
|
|
{
|
|
struct seq_file *m = file->private_data;
|
|
struct drm_i915_private *dev_priv = m->private;
|
|
char *tmpbuf;
|
|
int ret;
|
|
|
|
if (len == 0)
|
|
return 0;
|
|
|
|
if (len > PAGE_SIZE - 1) {
|
|
DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
|
|
PAGE_SIZE);
|
|
return -E2BIG;
|
|
}
|
|
|
|
tmpbuf = memdup_user_nul(ubuf, len);
|
|
if (IS_ERR(tmpbuf))
|
|
return PTR_ERR(tmpbuf);
|
|
|
|
ret = display_crc_ctl_parse(dev_priv, tmpbuf, len);
|
|
|
|
kfree(tmpbuf);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
*offp += len;
|
|
return len;
|
|
}
|
|
|
|
const struct file_operations i915_display_crc_ctl_fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = display_crc_ctl_open,
|
|
.read = seq_read,
|
|
.llseek = seq_lseek,
|
|
.release = single_release,
|
|
.write = display_crc_ctl_write
|
|
};
|
|
|
|
void intel_display_crc_init(struct drm_i915_private *dev_priv)
|
|
{
|
|
enum pipe pipe;
|
|
|
|
for_each_pipe(dev_priv, pipe) {
|
|
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
|
|
|
|
pipe_crc->opened = false;
|
|
spin_lock_init(&pipe_crc->lock);
|
|
init_waitqueue_head(&pipe_crc->wq);
|
|
}
|
|
}
|
|
|
|
int intel_pipe_crc_create(struct drm_minor *minor)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(minor->dev);
|
|
struct dentry *ent;
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
|
|
struct pipe_crc_info *info = &i915_pipe_crc_data[i];
|
|
|
|
info->dev_priv = dev_priv;
|
|
ent = debugfs_create_file(info->name, S_IRUGO,
|
|
minor->debugfs_root, info,
|
|
&i915_pipe_crc_fops);
|
|
if (!ent)
|
|
return -ENOMEM;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
|
|
size_t *values_cnt)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
|
|
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
|
|
enum intel_display_power_domain power_domain;
|
|
enum intel_pipe_crc_source source;
|
|
u32 val = 0; /* shut up gcc */
|
|
int ret = 0;
|
|
|
|
if (display_crc_ctl_parse_source(source_name, &source) < 0) {
|
|
DRM_DEBUG_DRIVER("unknown source %s\n", source_name);
|
|
return -EINVAL;
|
|
}
|
|
|
|
power_domain = POWER_DOMAIN_PIPE(crtc->index);
|
|
if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
|
|
DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
|
|
return -EIO;
|
|
}
|
|
|
|
ret = get_new_crc_ctl_reg(dev_priv, crtc->index, &source, &val, true);
|
|
if (ret != 0)
|
|
goto out;
|
|
|
|
pipe_crc->source = source;
|
|
I915_WRITE(PIPE_CRC_CTL(crtc->index), val);
|
|
POSTING_READ(PIPE_CRC_CTL(crtc->index));
|
|
|
|
if (!source) {
|
|
if (IS_G4X(dev_priv))
|
|
g4x_undo_pipe_scramble_reset(dev_priv, crtc->index);
|
|
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
|
|
vlv_undo_pipe_scramble_reset(dev_priv, crtc->index);
|
|
else if ((IS_HASWELL(dev_priv) ||
|
|
IS_BROADWELL(dev_priv)) && crtc->index == PIPE_A)
|
|
hsw_pipe_A_crc_wa(dev_priv, false);
|
|
}
|
|
|
|
pipe_crc->skipped = 0;
|
|
*values_cnt = 5;
|
|
|
|
out:
|
|
intel_display_power_put(dev_priv, power_domain);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void intel_crtc_enable_pipe_crc(struct intel_crtc *intel_crtc)
|
|
{
|
|
struct drm_crtc *crtc = &intel_crtc->base;
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
|
|
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
|
|
u32 val = 0;
|
|
|
|
if (!crtc->crc.opened)
|
|
return;
|
|
|
|
if (get_new_crc_ctl_reg(dev_priv, crtc->index, &pipe_crc->source, &val, false) < 0)
|
|
return;
|
|
|
|
/* Don't need pipe_crc->lock here, IRQs are not generated. */
|
|
pipe_crc->skipped = 0;
|
|
|
|
I915_WRITE(PIPE_CRC_CTL(crtc->index), val);
|
|
POSTING_READ(PIPE_CRC_CTL(crtc->index));
|
|
}
|
|
|
|
void intel_crtc_disable_pipe_crc(struct intel_crtc *intel_crtc)
|
|
{
|
|
struct drm_crtc *crtc = &intel_crtc->base;
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
|
|
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
|
|
|
|
/* Swallow crc's until we stop generating them. */
|
|
spin_lock_irq(&pipe_crc->lock);
|
|
pipe_crc->skipped = INT_MIN;
|
|
spin_unlock_irq(&pipe_crc->lock);
|
|
|
|
I915_WRITE(PIPE_CRC_CTL(crtc->index), 0);
|
|
POSTING_READ(PIPE_CRC_CTL(crtc->index));
|
|
synchronize_irq(dev_priv->drm.irq);
|
|
}
|