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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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c986a3d520
Make all definitions of the ColdFire Interrupt Source registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
370 lines
7.4 KiB
C
370 lines
7.4 KiB
C
/*
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* device.c -- common ColdFire SoC device support
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*
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* (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/spi/spi.h>
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#include <linux/gpio.h>
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#include <linux/fec.h>
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#include <asm/traps.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/mcfuart.h>
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#include <asm/mcfqspi.h>
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/*
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* All current ColdFire parts contain from 2, 3, 4 or 10 UARTS.
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*/
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static struct mcf_platform_uart mcf_uart_platform_data[] = {
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{
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.mapbase = MCFUART_BASE0,
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.irq = MCF_IRQ_UART0,
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},
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{
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.mapbase = MCFUART_BASE1,
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.irq = MCF_IRQ_UART1,
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},
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#ifdef MCFUART_BASE2
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{
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.mapbase = MCFUART_BASE2,
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.irq = MCF_IRQ_UART2,
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},
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#endif
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#ifdef MCFUART_BASE3
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{
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.mapbase = MCFUART_BASE3,
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.irq = MCF_IRQ_UART3,
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},
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#endif
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#ifdef MCFUART_BASE4
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{
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.mapbase = MCFUART_BASE4,
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.irq = MCF_IRQ_UART4,
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},
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#endif
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#ifdef MCFUART_BASE5
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{
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.mapbase = MCFUART_BASE5,
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.irq = MCF_IRQ_UART5,
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},
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#endif
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#ifdef MCFUART_BASE6
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{
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.mapbase = MCFUART_BASE6,
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.irq = MCF_IRQ_UART6,
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},
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#endif
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#ifdef MCFUART_BASE7
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{
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.mapbase = MCFUART_BASE7,
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.irq = MCF_IRQ_UART7,
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},
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#endif
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#ifdef MCFUART_BASE8
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{
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.mapbase = MCFUART_BASE8,
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.irq = MCF_IRQ_UART8,
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},
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#endif
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#ifdef MCFUART_BASE9
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{
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.mapbase = MCFUART_BASE9,
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.irq = MCF_IRQ_UART9,
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},
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#endif
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{ },
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};
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static struct platform_device mcf_uart = {
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.name = "mcfuart",
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.id = 0,
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.dev.platform_data = mcf_uart_platform_data,
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};
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#ifdef CONFIG_FEC
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#ifdef CONFIG_M5441x
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#define FEC_NAME "enet-fec"
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static struct fec_platform_data fec_pdata = {
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.phy = PHY_INTERFACE_MODE_RMII,
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};
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#define FEC_PDATA (&fec_pdata)
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#else
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#define FEC_NAME "fec"
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#define FEC_PDATA NULL
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#endif
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/*
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* Some ColdFire cores contain the Fast Ethernet Controller (FEC)
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* block. It is Freescale's own hardware block. Some ColdFires
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* have 2 of these.
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*/
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static struct resource mcf_fec0_resources[] = {
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{
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.start = MCFFEC_BASE0,
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.end = MCFFEC_BASE0 + MCFFEC_SIZE0 - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MCF_IRQ_FECRX0,
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.end = MCF_IRQ_FECRX0,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = MCF_IRQ_FECTX0,
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.end = MCF_IRQ_FECTX0,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = MCF_IRQ_FECENTC0,
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.end = MCF_IRQ_FECENTC0,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mcf_fec0 = {
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.name = FEC_NAME,
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.id = 0,
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.num_resources = ARRAY_SIZE(mcf_fec0_resources),
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.resource = mcf_fec0_resources,
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.dev.platform_data = FEC_PDATA,
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};
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#ifdef MCFFEC_BASE1
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static struct resource mcf_fec1_resources[] = {
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{
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.start = MCFFEC_BASE1,
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.end = MCFFEC_BASE1 + MCFFEC_SIZE1 - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MCF_IRQ_FECRX1,
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.end = MCF_IRQ_FECRX1,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = MCF_IRQ_FECTX1,
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.end = MCF_IRQ_FECTX1,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = MCF_IRQ_FECENTC1,
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.end = MCF_IRQ_FECENTC1,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mcf_fec1 = {
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.name = FEC_NAME,
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.id = 1,
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.num_resources = ARRAY_SIZE(mcf_fec1_resources),
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.resource = mcf_fec1_resources,
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.dev.platform_data = FEC_PDATA,
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};
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#endif /* MCFFEC_BASE1 */
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#endif /* CONFIG_FEC */
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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
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/*
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* The ColdFire QSPI module is an SPI protocol hardware block used
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* on a number of different ColdFire CPUs.
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*/
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static struct resource mcf_qspi_resources[] = {
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{
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.start = MCFQSPI_BASE,
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.end = MCFQSPI_BASE + MCFQSPI_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MCF_IRQ_QSPI,
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.end = MCF_IRQ_QSPI,
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.flags = IORESOURCE_IRQ,
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},
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};
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static int mcf_cs_setup(struct mcfqspi_cs_control *cs_control)
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{
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int status;
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status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
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if (status) {
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pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
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goto fail0;
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}
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status = gpio_direction_output(MCFQSPI_CS0, 1);
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if (status) {
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pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
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goto fail1;
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}
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status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
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if (status) {
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pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
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goto fail1;
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}
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status = gpio_direction_output(MCFQSPI_CS1, 1);
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if (status) {
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pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
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goto fail2;
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}
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status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
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if (status) {
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pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
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goto fail2;
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}
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status = gpio_direction_output(MCFQSPI_CS2, 1);
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if (status) {
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pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
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goto fail3;
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}
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#ifdef MCFQSPI_CS3
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status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
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if (status) {
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pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
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goto fail3;
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}
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status = gpio_direction_output(MCFQSPI_CS3, 1);
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if (status) {
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pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
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gpio_free(MCFQSPI_CS3);
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goto fail3;
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}
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#endif
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return 0;
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fail3:
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gpio_free(MCFQSPI_CS2);
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fail2:
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gpio_free(MCFQSPI_CS1);
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fail1:
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gpio_free(MCFQSPI_CS0);
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fail0:
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return status;
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}
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static void mcf_cs_teardown(struct mcfqspi_cs_control *cs_control)
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{
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#ifdef MCFQSPI_CS3
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gpio_free(MCFQSPI_CS3);
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#endif
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gpio_free(MCFQSPI_CS2);
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gpio_free(MCFQSPI_CS1);
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gpio_free(MCFQSPI_CS0);
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}
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static void mcf_cs_select(struct mcfqspi_cs_control *cs_control,
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u8 chip_select, bool cs_high)
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{
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switch (chip_select) {
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case 0:
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gpio_set_value(MCFQSPI_CS0, cs_high);
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break;
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case 1:
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gpio_set_value(MCFQSPI_CS1, cs_high);
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break;
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case 2:
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gpio_set_value(MCFQSPI_CS2, cs_high);
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break;
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#ifdef MCFQSPI_CS3
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case 3:
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gpio_set_value(MCFQSPI_CS3, cs_high);
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break;
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#endif
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}
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}
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static void mcf_cs_deselect(struct mcfqspi_cs_control *cs_control,
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u8 chip_select, bool cs_high)
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{
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switch (chip_select) {
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case 0:
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gpio_set_value(MCFQSPI_CS0, !cs_high);
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break;
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case 1:
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gpio_set_value(MCFQSPI_CS1, !cs_high);
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break;
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case 2:
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gpio_set_value(MCFQSPI_CS2, !cs_high);
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break;
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#ifdef MCFQSPI_CS3
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case 3:
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gpio_set_value(MCFQSPI_CS3, !cs_high);
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break;
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#endif
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}
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}
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static struct mcfqspi_cs_control mcf_cs_control = {
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.setup = mcf_cs_setup,
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.teardown = mcf_cs_teardown,
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.select = mcf_cs_select,
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.deselect = mcf_cs_deselect,
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};
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static struct mcfqspi_platform_data mcf_qspi_data = {
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.bus_num = 0,
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.num_chipselect = 4,
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.cs_control = &mcf_cs_control,
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};
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static struct platform_device mcf_qspi = {
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.name = "mcfqspi",
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.id = 0,
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.num_resources = ARRAY_SIZE(mcf_qspi_resources),
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.resource = mcf_qspi_resources,
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.dev.platform_data = &mcf_qspi_data,
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};
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#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
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static struct platform_device *mcf_devices[] __initdata = {
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&mcf_uart,
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#ifdef CONFIG_FEC
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&mcf_fec0,
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#ifdef MCFFEC_BASE1
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&mcf_fec1,
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#endif
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#endif
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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
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&mcf_qspi,
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#endif
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};
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/*
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* Some ColdFire UARTs let you set the IRQ line to use.
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*/
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static void __init mcf_uart_set_irq(void)
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{
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#ifdef MCFUART_UIVR
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/* UART0 interrupt setup */
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writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCFSIM_UART1ICR);
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writeb(MCF_IRQ_UART0, MCFUART_BASE0 + MCFUART_UIVR);
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mcf_mapirq2imr(MCF_IRQ_UART0, MCFINTC_UART0);
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/* UART1 interrupt setup */
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writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCFSIM_UART2ICR);
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writeb(MCF_IRQ_UART1, MCFUART_BASE1 + MCFUART_UIVR);
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mcf_mapirq2imr(MCF_IRQ_UART1, MCFINTC_UART1);
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#endif
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}
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static int __init mcf_init_devices(void)
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{
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mcf_uart_set_irq();
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platform_add_devices(mcf_devices, ARRAY_SIZE(mcf_devices));
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return 0;
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}
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arch_initcall(mcf_init_devices);
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