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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e87c09a899
Output a table of the kernel memory regions at boot time.
This is taken directly from the ARM architecture code that does this.
The table looks like this:
Virtual kernel memory layout:
vector : 0x00000000 - 0x00000400 ( 0 KiB)
kmap : 0xd0000000 - 0xe0000000 ( 256 MiB)
vmalloc : 0xc0000000 - 0xcfffffff ( 255 MiB)
lowmem : 0x00000000 - 0x02000000 ( 32 MiB)
.init : 0x00128000 - 0x00134000 ( 48 KiB)
.text : 0x00020000 - 0x00118d54 ( 996 KiB)
.data : 0x00118d60 - 0x00126000 ( 53 KiB)
.bss : 0x00134000 - 0x001413e0 ( 53 KiB)
This has been very useful while debugging the ColdFire virtual memory
support code. But in general I think it is nice to know extacly where
the kernel has layed everything out on boot.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
273 lines
8.3 KiB
C
273 lines
8.3 KiB
C
/*
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* linux/include/asm/traps.h
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*
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* Copyright (C) 1993 Hamish Macdonald
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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#ifndef _M68K_TRAPS_H
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#define _M68K_TRAPS_H
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#ifndef __ASSEMBLY__
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#include <linux/linkage.h>
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#include <asm/ptrace.h>
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typedef void (*e_vector)(void);
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extern e_vector vectors[];
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extern e_vector *_ramvec;
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asmlinkage void auto_inthandler(void);
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asmlinkage void user_inthandler(void);
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asmlinkage void bad_inthandler(void);
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#endif
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#define VEC_RESETSP (0)
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#define VEC_RESETPC (1)
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#define VEC_BUSERR (2)
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#define VEC_ADDRERR (3)
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#define VEC_ILLEGAL (4)
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#define VEC_ZERODIV (5)
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#define VEC_CHK (6)
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#define VEC_TRAP (7)
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#define VEC_PRIV (8)
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#define VEC_TRACE (9)
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#define VEC_LINE10 (10)
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#define VEC_LINE11 (11)
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#define VEC_RESV12 (12)
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#define VEC_COPROC (13)
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#define VEC_FORMAT (14)
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#define VEC_UNINT (15)
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#define VEC_RESV16 (16)
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#define VEC_RESV17 (17)
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#define VEC_RESV18 (18)
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#define VEC_RESV19 (19)
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#define VEC_RESV20 (20)
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#define VEC_RESV21 (21)
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#define VEC_RESV22 (22)
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#define VEC_RESV23 (23)
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#define VEC_SPUR (24)
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#define VEC_INT1 (25)
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#define VEC_INT2 (26)
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#define VEC_INT3 (27)
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#define VEC_INT4 (28)
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#define VEC_INT5 (29)
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#define VEC_INT6 (30)
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#define VEC_INT7 (31)
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#define VEC_SYS (32)
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#define VEC_TRAP1 (33)
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#define VEC_TRAP2 (34)
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#define VEC_TRAP3 (35)
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#define VEC_TRAP4 (36)
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#define VEC_TRAP5 (37)
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#define VEC_TRAP6 (38)
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#define VEC_TRAP7 (39)
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#define VEC_TRAP8 (40)
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#define VEC_TRAP9 (41)
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#define VEC_TRAP10 (42)
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#define VEC_TRAP11 (43)
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#define VEC_TRAP12 (44)
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#define VEC_TRAP13 (45)
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#define VEC_TRAP14 (46)
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#define VEC_TRAP15 (47)
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#define VEC_FPBRUC (48)
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#define VEC_FPIR (49)
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#define VEC_FPDIVZ (50)
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#define VEC_FPUNDER (51)
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#define VEC_FPOE (52)
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#define VEC_FPOVER (53)
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#define VEC_FPNAN (54)
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#define VEC_FPUNSUP (55)
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#define VEC_MMUCFG (56)
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#define VEC_MMUILL (57)
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#define VEC_MMUACC (58)
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#define VEC_RESV59 (59)
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#define VEC_UNIMPEA (60)
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#define VEC_UNIMPII (61)
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#define VEC_RESV62 (62)
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#define VEC_RESV63 (63)
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#define VEC_USER (64)
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#define VECOFF(vec) ((vec)<<2)
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#ifndef __ASSEMBLY__
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/* Status register bits */
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#define PS_T (0x8000)
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#define PS_S (0x2000)
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#define PS_M (0x1000)
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#define PS_C (0x0001)
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/* bits for 68020/68030 special status word */
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#define FC (0x8000)
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#define FB (0x4000)
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#define RC (0x2000)
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#define RB (0x1000)
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#define DF (0x0100)
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#define RM (0x0080)
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#define RW (0x0040)
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#define SZ (0x0030)
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#define DFC (0x0007)
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/* bits for 68030 MMU status register (mmusr,psr) */
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#define MMU_B (0x8000) /* bus error */
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#define MMU_L (0x4000) /* limit violation */
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#define MMU_S (0x2000) /* supervisor violation */
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#define MMU_WP (0x0800) /* write-protected */
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#define MMU_I (0x0400) /* invalid descriptor */
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#define MMU_M (0x0200) /* ATC entry modified */
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#define MMU_T (0x0040) /* transparent translation */
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#define MMU_NUM (0x0007) /* number of levels traversed */
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/* bits for 68040 special status word */
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#define CP_040 (0x8000)
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#define CU_040 (0x4000)
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#define CT_040 (0x2000)
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#define CM_040 (0x1000)
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#define MA_040 (0x0800)
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#define ATC_040 (0x0400)
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#define LK_040 (0x0200)
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#define RW_040 (0x0100)
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#define SIZ_040 (0x0060)
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#define TT_040 (0x0018)
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#define TM_040 (0x0007)
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/* bits for 68040 write back status word */
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#define WBV_040 (0x80)
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#define WBSIZ_040 (0x60)
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#define WBBYT_040 (0x20)
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#define WBWRD_040 (0x40)
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#define WBLNG_040 (0x00)
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#define WBTT_040 (0x18)
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#define WBTM_040 (0x07)
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/* bus access size codes */
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#define BA_SIZE_BYTE (0x20)
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#define BA_SIZE_WORD (0x40)
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#define BA_SIZE_LONG (0x00)
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#define BA_SIZE_LINE (0x60)
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/* bus access transfer type codes */
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#define BA_TT_MOVE16 (0x08)
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/* bits for 68040 MMU status register (mmusr) */
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#define MMU_B_040 (0x0800)
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#define MMU_G_040 (0x0400)
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#define MMU_S_040 (0x0080)
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#define MMU_CM_040 (0x0060)
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#define MMU_M_040 (0x0010)
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#define MMU_WP_040 (0x0004)
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#define MMU_T_040 (0x0002)
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#define MMU_R_040 (0x0001)
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/* bits in the 68060 fault status long word (FSLW) */
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#define MMU060_MA (0x08000000) /* misaligned */
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#define MMU060_LK (0x02000000) /* locked transfer */
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#define MMU060_RW (0x01800000) /* read/write */
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# define MMU060_RW_W (0x00800000) /* write */
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# define MMU060_RW_R (0x01000000) /* read */
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# define MMU060_RW_RMW (0x01800000) /* read/modify/write */
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# define MMU060_W (0x00800000) /* general write, includes rmw */
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#define MMU060_SIZ (0x00600000) /* transfer size */
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#define MMU060_TT (0x00180000) /* transfer type (TT) bits */
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#define MMU060_TM (0x00070000) /* transfer modifier (TM) bits */
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#define MMU060_IO (0x00008000) /* instruction or operand */
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#define MMU060_PBE (0x00004000) /* push buffer bus error */
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#define MMU060_SBE (0x00002000) /* store buffer bus error */
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#define MMU060_PTA (0x00001000) /* pointer A fault */
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#define MMU060_PTB (0x00000800) /* pointer B fault */
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#define MMU060_IL (0x00000400) /* double indirect descr fault */
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#define MMU060_PF (0x00000200) /* page fault (invalid descr) */
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#define MMU060_SP (0x00000100) /* supervisor protection */
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#define MMU060_WP (0x00000080) /* write protection */
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#define MMU060_TWE (0x00000040) /* bus error on table search */
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#define MMU060_RE (0x00000020) /* bus error on read */
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#define MMU060_WE (0x00000010) /* bus error on write */
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#define MMU060_TTR (0x00000008) /* error caused by TTR translation */
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#define MMU060_BPE (0x00000004) /* branch prediction error */
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#define MMU060_SEE (0x00000001) /* software emulated error */
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/* cases of missing or invalid descriptors */
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#define MMU060_DESC_ERR (MMU060_PTA | MMU060_PTB | \
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MMU060_IL | MMU060_PF)
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/* bits that indicate real errors */
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#define MMU060_ERR_BITS (MMU060_PBE | MMU060_SBE | MMU060_DESC_ERR | MMU060_SP | \
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MMU060_WP | MMU060_TWE | MMU060_RE | MMU060_WE)
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/* structure for stack frames */
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struct frame {
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struct pt_regs ptregs;
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union {
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struct {
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unsigned long iaddr; /* instruction address */
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} fmt2;
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struct {
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unsigned long effaddr; /* effective address */
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} fmt3;
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struct {
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unsigned long effaddr; /* effective address */
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unsigned long pc; /* pc of faulted instr */
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} fmt4;
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struct {
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unsigned long effaddr; /* effective address */
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unsigned short ssw; /* special status word */
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unsigned short wb3s; /* write back 3 status */
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unsigned short wb2s; /* write back 2 status */
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unsigned short wb1s; /* write back 1 status */
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unsigned long faddr; /* fault address */
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unsigned long wb3a; /* write back 3 address */
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unsigned long wb3d; /* write back 3 data */
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unsigned long wb2a; /* write back 2 address */
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unsigned long wb2d; /* write back 2 data */
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unsigned long wb1a; /* write back 1 address */
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unsigned long wb1dpd0; /* write back 1 data/push data 0*/
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unsigned long pd1; /* push data 1*/
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unsigned long pd2; /* push data 2*/
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unsigned long pd3; /* push data 3*/
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} fmt7;
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struct {
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unsigned long iaddr; /* instruction address */
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unsigned short int1[4]; /* internal registers */
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} fmt9;
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struct {
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unsigned short int1;
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unsigned short ssw; /* special status word */
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unsigned short isc; /* instruction stage c */
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unsigned short isb; /* instruction stage b */
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unsigned long daddr; /* data cycle fault address */
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unsigned short int2[2];
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unsigned long dobuf; /* data cycle output buffer */
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unsigned short int3[2];
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} fmta;
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struct {
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unsigned short int1;
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unsigned short ssw; /* special status word */
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unsigned short isc; /* instruction stage c */
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unsigned short isb; /* instruction stage b */
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unsigned long daddr; /* data cycle fault address */
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unsigned short int2[2];
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unsigned long dobuf; /* data cycle output buffer */
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unsigned short int3[4];
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unsigned long baddr; /* stage B address */
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unsigned short int4[2];
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unsigned long dibuf; /* data cycle input buffer */
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unsigned short int5[3];
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unsigned ver : 4; /* stack frame version # */
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unsigned int6:12;
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unsigned short int7[18];
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} fmtb;
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} un;
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};
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#endif /* __ASSEMBLY__ */
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#endif /* _M68K_TRAPS_H */
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