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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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5320b50797
PAMU bypass enable register added to the ccsr_guts structure. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
190 lines
7.8 KiB
C
190 lines
7.8 KiB
C
/**
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* Freecale 85xx and 86xx Global Utilties register set
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*
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* Authors: Jeff Brown
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* Timur Tabi <timur@freescale.com>
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*
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* Copyright 2004,2007,2012 Freescale Semiconductor, Inc
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __ASM_POWERPC_FSL_GUTS_H__
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#define __ASM_POWERPC_FSL_GUTS_H__
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#ifdef __KERNEL__
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/**
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* Global Utility Registers.
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*
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* Not all registers defined in this structure are available on all chips, so
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* you are expected to know whether a given register actually exists on your
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* chip before you access it.
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*
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* Also, some registers are similar on different chips but have slightly
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* different names. In these cases, one name is chosen to avoid extraneous
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* #ifdefs.
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*/
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struct ccsr_guts {
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__be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
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__be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
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__be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
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__be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
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__be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
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__be32 pordevsr2; /* 0x.0014 - POR device status register 2 */
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u8 res018[0x20 - 0x18];
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__be32 porcir; /* 0x.0020 - POR Configuration Information Register */
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u8 res024[0x30 - 0x24];
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__be32 gpiocr; /* 0x.0030 - GPIO Control Register */
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u8 res034[0x40 - 0x34];
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__be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
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u8 res044[0x50 - 0x44];
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__be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */
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u8 res054[0x60 - 0x54];
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__be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
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__be32 pmuxcr2; /* 0x.0064 - Alternate function signal multiplex control 2 */
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__be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
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u8 res06c[0x70 - 0x6c];
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__be32 devdisr; /* 0x.0070 - Device Disable Control */
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#define CCSR_GUTS_DEVDISR_TB1 0x00001000
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#define CCSR_GUTS_DEVDISR_TB0 0x00004000
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__be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
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u8 res078[0x7c - 0x78];
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__be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */
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__be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
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__be32 pmrccr; /* 0x.0084 - Power Management Reset Counter Configuration Register */
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__be32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter Configuration Register */
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__be32 pmcdr; /* 0x.008c - 4Power management clock disable register */
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__be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
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__be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */
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__be32 ectrstcr; /* 0x.0098 - Exception reset control register */
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__be32 autorstsr; /* 0x.009c - Automatic reset status register */
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__be32 pvr; /* 0x.00a0 - Processor Version Register */
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__be32 svr; /* 0x.00a4 - System Version Register */
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u8 res0a8[0xb0 - 0xa8];
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__be32 rstcr; /* 0x.00b0 - Reset Control Register */
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u8 res0b4[0xc0 - 0xb4];
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__be32 iovselsr; /* 0x.00c0 - I/O voltage select status register
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Called 'elbcvselcr' on 86xx SOCs */
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u8 res0c4[0x224 - 0xc4];
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__be32 iodelay1; /* 0x.0224 - IO delay control register 1 */
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__be32 iodelay2; /* 0x.0228 - IO delay control register 2 */
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u8 res22c[0x604 - 0x22c];
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__be32 pamubypenr; /* 0x.604 - PAMU bypass enable register */
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u8 res608[0x800 - 0x608];
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__be32 clkdvdr; /* 0x.0800 - Clock Divide Register */
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u8 res804[0x900 - 0x804];
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__be32 ircr; /* 0x.0900 - Infrared Control Register */
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u8 res904[0x908 - 0x904];
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__be32 dmacr; /* 0x.0908 - DMA Control Register */
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u8 res90c[0x914 - 0x90c];
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__be32 elbccr; /* 0x.0914 - eLBC Control Register */
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u8 res918[0xb20 - 0x918];
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__be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
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__be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
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__be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
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u8 resb2c[0xe00 - 0xb2c];
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__be32 clkocr; /* 0x.0e00 - Clock Out Select Register */
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u8 rese04[0xe10 - 0xe04];
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__be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
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u8 rese14[0xe20 - 0xe14];
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__be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
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__be32 cpfor; /* 0x.0e24 - L2 charge pump fuse override register */
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u8 rese28[0xf04 - 0xe28];
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__be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
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__be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
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u8 resf0c[0xf2c - 0xf0c];
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__be32 itcr; /* 0x.0f2c - Internal transaction control register */
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u8 resf30[0xf40 - 0xf30];
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__be32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
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__be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
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} __attribute__ ((packed));
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/* Alternate function signal multiplex control */
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#define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
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#ifdef CONFIG_PPC_86xx
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#define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */
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#define CCSR_GUTS_DMACR_DEV_IR 1 /* DMA controller/channel set to IR */
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/*
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* Set the DMACR register in the GUTS
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*
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* The DMACR register determines the source of initiated transfers for each
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* channel on each DMA controller. Rather than have a bunch of repetitive
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* macros for the bit patterns, we just have a function that calculates
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* them.
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*
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* guts: Pointer to GUTS structure
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* co: The DMA controller (0 or 1)
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* ch: The channel on the DMA controller (0, 1, 2, or 3)
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* device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
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*/
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static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
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unsigned int co, unsigned int ch, unsigned int device)
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{
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unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
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clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift);
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}
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#define CCSR_GUTS_PMUXCR_LDPSEL 0x00010000
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#define CCSR_GUTS_PMUXCR_SSI1_MASK 0x0000C000 /* Bitmask for SSI1 */
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#define CCSR_GUTS_PMUXCR_SSI1_LA 0x00000000 /* Latched address */
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#define CCSR_GUTS_PMUXCR_SSI1_HI 0x00004000 /* High impedance */
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#define CCSR_GUTS_PMUXCR_SSI1_SSI 0x00008000 /* Used for SSI1 */
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#define CCSR_GUTS_PMUXCR_SSI2_MASK 0x00003000 /* Bitmask for SSI2 */
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#define CCSR_GUTS_PMUXCR_SSI2_LA 0x00000000 /* Latched address */
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#define CCSR_GUTS_PMUXCR_SSI2_HI 0x00001000 /* High impedance */
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#define CCSR_GUTS_PMUXCR_SSI2_SSI 0x00002000 /* Used for SSI2 */
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#define CCSR_GUTS_PMUXCR_LA_22_25_LA 0x00000000 /* Latched Address */
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#define CCSR_GUTS_PMUXCR_LA_22_25_HI 0x00000400 /* High impedance */
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#define CCSR_GUTS_PMUXCR_DBGDRV 0x00000200 /* Signals not driven */
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#define CCSR_GUTS_PMUXCR_DMA2_0 0x00000008
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#define CCSR_GUTS_PMUXCR_DMA2_3 0x00000004
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#define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002
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#define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001
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/*
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* Set the DMA external control bits in the GUTS
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*
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* The DMA external control bits in the PMUXCR are only meaningful for
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* channels 0 and 3. Any other channels are ignored.
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*
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* guts: Pointer to GUTS structure
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* co: The DMA controller (0 or 1)
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* ch: The channel on the DMA controller (0, 1, 2, or 3)
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* value: the new value for the bit (0 or 1)
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*/
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static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
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unsigned int co, unsigned int ch, unsigned int value)
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{
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if ((ch == 0) || (ch == 3)) {
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unsigned int shift = 2 * (co + 1) - (ch & 1) - 1;
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clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift);
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}
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}
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#define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000
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#define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000
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#define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000
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#define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25
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#define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK 0x06000000
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#define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \
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(((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT)
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#define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT 16
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#define CCSR_GUTS_CLKDVDR_PXCLK_MASK 0x001F0000
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#define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT)
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#define CCSR_GUTS_CLKDVDR_SSICLK_MASK 0x000000FF
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#define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK)
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#endif
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#endif
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#endif
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