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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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783c8f4c84
Implement fuse driver for Tegra20, Tegra30, Tegra114 and Tegra124. This replaces functionality previously provided in arch/arm/mach-tegra, which is removed in this patch. While at it, move the only user of the global tegra_revision variable over to tegra_sku_info.revision and export tegra_fuse_readl() to allow drivers to read calibration fuses. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
111 lines
2.7 KiB
C
111 lines
2.7 KiB
C
/*
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* Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/bug.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <soc/tegra/fuse.h>
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#include "fuse.h"
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#define CORE_PROCESS_CORNERS 2
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#define CPU_PROCESS_CORNERS 2
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enum {
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THRESHOLD_INDEX_0,
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THRESHOLD_INDEX_1,
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THRESHOLD_INDEX_COUNT,
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};
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static const u32 __initconst core_process_speedos[][CORE_PROCESS_CORNERS] = {
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{1123, UINT_MAX},
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{0, UINT_MAX},
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};
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static const u32 __initconst cpu_process_speedos[][CPU_PROCESS_CORNERS] = {
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{1695, UINT_MAX},
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{0, UINT_MAX},
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};
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static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info,
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int *threshold)
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{
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u32 tmp;
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u32 sku = sku_info->sku_id;
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enum tegra_revision rev = sku_info->revision;
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switch (sku) {
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case 0x00:
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case 0x10:
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case 0x05:
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case 0x06:
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sku_info->cpu_speedo_id = 1;
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sku_info->soc_speedo_id = 0;
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*threshold = THRESHOLD_INDEX_0;
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break;
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case 0x03:
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case 0x04:
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sku_info->cpu_speedo_id = 2;
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sku_info->soc_speedo_id = 1;
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*threshold = THRESHOLD_INDEX_1;
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break;
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default:
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pr_err("Tegra Unknown SKU %d\n", sku);
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sku_info->cpu_speedo_id = 0;
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sku_info->soc_speedo_id = 0;
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*threshold = THRESHOLD_INDEX_0;
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break;
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}
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if (rev == TEGRA_REVISION_A01) {
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tmp = tegra30_fuse_readl(0x270) << 1;
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tmp |= tegra30_fuse_readl(0x26c);
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if (!tmp)
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sku_info->cpu_speedo_id = 0;
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}
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}
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void __init tegra114_init_speedo_data(struct tegra_sku_info *sku_info)
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{
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u32 cpu_speedo_val;
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u32 core_speedo_val;
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int threshold;
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int i;
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BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
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THRESHOLD_INDEX_COUNT);
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BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
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THRESHOLD_INDEX_COUNT);
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rev_sku_to_speedo_ids(sku_info, &threshold);
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cpu_speedo_val = tegra30_fuse_readl(0x12c) + 1024;
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core_speedo_val = tegra30_fuse_readl(0x134);
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for (i = 0; i < CPU_PROCESS_CORNERS; i++)
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if (cpu_speedo_val < cpu_process_speedos[threshold][i])
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break;
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sku_info->cpu_process_id = i;
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for (i = 0; i < CORE_PROCESS_CORNERS; i++)
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if (core_speedo_val < core_process_speedos[threshold][i])
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break;
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sku_info->core_process_id = i;
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}
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