mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 22:35:14 +07:00
fd5e5dd56a
This patch enables PCIe0 and PCIe4 for NS2 by adding appropriate DT nodes in NS2 DT. Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
449 lines
12 KiB
Plaintext
449 lines
12 KiB
Plaintext
/*
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* BSD LICENSE
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*
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* Copyright(c) 2015 Broadcom Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Broadcom Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/bcm-ns2.h>
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/memreserve/ 0x84b00000 0x00000008;
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/ {
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compatible = "brcm,ns2";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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A57_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0 0>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x84b00000>;
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next-level-cache = <&CLUSTER0_L2>;
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};
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A57_1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0 1>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x84b00000>;
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next-level-cache = <&CLUSTER0_L2>;
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};
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A57_2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0 2>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x84b00000>;
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next-level-cache = <&CLUSTER0_L2>;
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};
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A57_3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0 3>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x84b00000>;
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next-level-cache = <&CLUSTER0_L2>;
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};
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CLUSTER0_L2: l2-cache@000 {
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compatible = "cache";
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
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IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
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IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
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IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
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IRQ_TYPE_EDGE_RISING)>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&A57_0>,
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<&A57_1>,
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<&A57_2>,
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<&A57_3>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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osc: oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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};
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iprocmed: iprocmed {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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iprocslow: iprocslow {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
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clock-div = <4>;
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clock-mult = <1>;
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};
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};
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pcie0: pcie@20020000 {
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compatible = "brcm,iproc-pcie";
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reg = <0 0x20020000 0 0x1000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 281 IRQ_TYPE_NONE>;
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linux,pci-domain = <0>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
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brcm,pcie-ob;
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brcm,pcie-ob-oarr-size;
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brcm,pcie-ob-axi-offset = <0x00000000>;
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brcm,pcie-ob-window-size = <256>;
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status = "disabled";
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msi-parent = <&msi0>;
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msi0: msi@20020000 {
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compatible = "brcm,iproc-msi";
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msi-controller;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 277 IRQ_TYPE_NONE>,
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<GIC_SPI 278 IRQ_TYPE_NONE>,
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<GIC_SPI 279 IRQ_TYPE_NONE>,
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<GIC_SPI 280 IRQ_TYPE_NONE>;
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brcm,num-eq-region = <1>;
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brcm,num-msi-msg-region = <1>;
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};
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};
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pcie4: pcie@50020000 {
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compatible = "brcm,iproc-pcie";
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reg = <0 0x50020000 0 0x1000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 305 IRQ_TYPE_NONE>;
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linux,pci-domain = <4>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
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brcm,pcie-ob;
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brcm,pcie-ob-oarr-size;
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brcm,pcie-ob-axi-offset = <0x30000000>;
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brcm,pcie-ob-window-size = <256>;
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status = "disabled";
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msi-parent = <&msi4>;
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msi4: msi@50020000 {
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compatible = "brcm,iproc-msi";
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msi-controller;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 301 IRQ_TYPE_NONE>,
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<GIC_SPI 302 IRQ_TYPE_NONE>,
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<GIC_SPI 303 IRQ_TYPE_NONE>,
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<GIC_SPI 304 IRQ_TYPE_NONE>;
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};
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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smmu: mmu@64000000 {
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compatible = "arm,mmu-500";
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reg = <0x64000000 0x40000>;
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#global-interrupts = <2>;
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interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
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mmu-masters;
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};
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lcpll_ddr: lcpll_ddr@6501d058 {
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#clock-cells = <1>;
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compatible = "brcm,ns2-lcpll-ddr";
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reg = <0x6501d058 0x20>,
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<0x6501c020 0x4>,
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<0x6501d04c 0x4>;
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clocks = <&osc>;
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clock-output-names = "lcpll_ddr", "pcie_sata_usb",
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"ddr", "ddr_ch2_unused",
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"ddr_ch3_unused", "ddr_ch4_unused",
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"ddr_ch5_unused";
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};
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lcpll_ports: lcpll_ports@6501d078 {
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#clock-cells = <1>;
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compatible = "brcm,ns2-lcpll-ports";
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reg = <0x6501d078 0x20>,
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<0x6501c020 0x4>,
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<0x6501d054 0x4>;
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clocks = <&osc>;
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clock-output-names = "lcpll_ports", "wan", "rgmii",
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"ports_ch2_unused",
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"ports_ch3_unused",
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"ports_ch4_unused",
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"ports_ch5_unused";
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};
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genpll_scr: genpll_scr@6501d098 {
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#clock-cells = <1>;
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compatible = "brcm,ns2-genpll-scr";
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reg = <0x6501d098 0x32>,
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<0x6501c020 0x4>,
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<0x6501d044 0x4>;
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clocks = <&osc>;
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clock-output-names = "genpll_scr", "scr", "fs",
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"audio_ref", "scr_ch3_unused",
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"scr_ch4_unused", "scr_ch5_unused";
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};
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genpll_sw: genpll_sw@6501d0c4 {
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#clock-cells = <1>;
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compatible = "brcm,ns2-genpll-sw";
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reg = <0x6501d0c4 0x32>,
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<0x6501c020 0x4>,
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<0x6501d044 0x4>;
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clocks = <&osc>;
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clock-output-names = "genpll_sw", "rpe", "250", "nic",
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"chimp", "port", "sdio";
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};
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crmu: crmu@65024000 {
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compatible = "syscon";
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reg = <0x65024000 0x100>;
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};
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reboot@65024000 {
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compatible ="syscon-reboot";
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regmap = <&crmu>;
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offset = <0x90>;
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mask = <0xfffffffd>;
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};
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gic: interrupt-controller@65210000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x65210000 0x1000>,
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<0x65220000 0x1000>,
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<0x65240000 0x2000>,
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<0x65260000 0x1000>;
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};
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timer0: timer@66030000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x66030000 0x1000>;
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interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>,
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<&iprocslow>,
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<&iprocslow>;
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clock-names = "timer1", "timer2", "apb_pclk";
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};
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timer1: timer@66040000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x66040000 0x1000>;
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interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>,
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<&iprocslow>,
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<&iprocslow>;
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clock-names = "timer1", "timer2", "apb_pclk";
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};
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timer2: timer@66050000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x66050000 0x1000>;
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interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>,
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<&iprocslow>,
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<&iprocslow>;
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clock-names = "timer1", "timer2", "apb_pclk";
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};
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timer3: timer@66060000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x66060000 0x1000>;
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interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>,
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<&iprocslow>,
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<&iprocslow>;
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clock-names = "timer1", "timer2", "apb_pclk";
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};
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i2c0: i2c@66080000 {
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compatible = "brcm,iproc-i2c";
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reg = <0x66080000 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 394 IRQ_TYPE_NONE>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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wdt0: watchdog@66090000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x66090000 0x1000>;
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interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>, <&iprocslow>;
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clock-names = "wdogclk", "apb_pclk";
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};
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i2c1: i2c@660b0000 {
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compatible = "brcm,iproc-i2c";
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reg = <0x660b0000 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 395 IRQ_TYPE_NONE>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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uart3: serial@66130000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x66130000 0x100>;
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interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc>;
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status = "disabled";
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};
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hwrng: hwrng@66220000 {
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compatible = "brcm,iproc-rng200";
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reg = <0x66220000 0x28>;
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};
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sdio0: sdhci@66420000 {
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compatible = "brcm,sdhci-iproc-cygnus";
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reg = <0x66420000 0x100>;
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interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
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bus-width = <8>;
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clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
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status = "disabled";
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};
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sdio1: sdhci@66430000 {
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compatible = "brcm,sdhci-iproc-cygnus";
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reg = <0x66430000 0x100>;
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interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
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bus-width = <8>;
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clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
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status = "disabled";
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};
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nand: nand@66460000 {
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compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
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reg = <0x66460000 0x600>,
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<0x67015408 0x600>,
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<0x66460f00 0x20>;
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reg-names = "nand", "iproc-idm", "iproc-ext";
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interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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brcm,nand-has-wp;
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};
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};
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};
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