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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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741e3a89de
This allows us to remove cpu_is_omap calls from init_irq functions. There should not be any need for cpu_is_omap calls as at this point. During the timer init we only care about SoC generation, and not about subrevisions. The main reason for the patch is that we want to initialize only minimal omap specific code from the init_early call. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Kevin Hilman <khilman@ti.com>
114 lines
2.6 KiB
C
114 lines
2.6 KiB
C
/*
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* OMAP4 specific common source file.
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*
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* Copyright (C) 2010 Texas Instruments, Inc.
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* Author:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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*
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* This program is free software,you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <asm/hardware/gic.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <plat/irqs.h>
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#include <mach/hardware.h>
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#include <mach/omap4-common.h>
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#ifdef CONFIG_CACHE_L2X0
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void __iomem *l2cache_base;
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#endif
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void __iomem *gic_dist_base_addr;
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void __init gic_init_irq(void)
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{
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/* Static mapping, never released */
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gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
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BUG_ON(!gic_dist_base_addr);
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/* Static mapping, never released */
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omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
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BUG_ON(!omap_irq_base);
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gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
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}
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#ifdef CONFIG_CACHE_L2X0
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static void omap4_l2x0_disable(void)
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{
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/* Disable PL310 L2 Cache controller */
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omap_smc1(0x102, 0x0);
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}
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static void omap4_l2x0_set_debug(unsigned long val)
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{
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/* Program PL310 L2 Cache controller debug register */
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omap_smc1(0x100, val);
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}
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static int __init omap_l2_cache_init(void)
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{
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u32 aux_ctrl = 0;
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/*
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* To avoid code running on other OMAPs in
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* multi-omap builds
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*/
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if (!cpu_is_omap44xx())
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return -ENODEV;
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/* Static mapping, never released */
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l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
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BUG_ON(!l2cache_base);
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/*
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* 16-way associativity, parity disabled
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* Way size - 32KB (es1.0)
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* Way size - 64KB (es2.0 +)
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*/
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aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
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(0x1 << 25) |
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(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
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(0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
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if (omap_rev() == OMAP4430_REV_ES1_0) {
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aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
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} else {
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aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
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(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
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(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
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(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
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(1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
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}
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if (omap_rev() != OMAP4430_REV_ES1_0)
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omap_smc1(0x109, aux_ctrl);
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/* Enable PL310 L2 Cache controller */
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omap_smc1(0x102, 0x1);
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l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
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/*
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* Override default outer_cache.disable with a OMAP4
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* specific one
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*/
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outer_cache.disable = omap4_l2x0_disable;
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outer_cache.set_debug = omap4_l2x0_set_debug;
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return 0;
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}
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early_initcall(omap_l2_cache_init);
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#endif
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