Roger Quadros 032d774575 ARM: dts: dra7-clock: Add "l3init_960m_gfclk" clock gate ... This clock gate description is missing in the older Reference manuals. It is present on the SoC to provide 960MHz reference clock to the internal USB PHYs. Reference: DRA75x_DRA74x_ES1.1_NDA_TRM_vO.pdf, pg. 900, Table 3-812. CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL Use l3init_960m_gfclk as parent of usb_otg_ss1_refclk960m and usb_otg_ss2_refclk960m. CC: Benoît Cousson <bcousson@baylibre.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>		2014-05-14 14:39:34 -07:00
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bootp
compressed	ARM: 7992/1: boot: compressed: ignore bswapsdi2.S	2014-03-07 22:04:10 +00:00
dts	ARM: dts: dra7-clock: Add "l3init_960m_gfclk" clock gate	2014-05-14 14:39:34 -07:00
.gitignore
install.sh
Makefile