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292816a637
Follow the recent trend for the license description, and also fix the wrongly stated X11 to MIT. As already pointed on the DT ML, the X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
258 lines
6.0 KiB
Plaintext
258 lines
6.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2016 Marvell Technology Group Ltd.
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*
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* Device Tree file for Marvell Armada AP806.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/dts-v1/;
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/ {
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model = "Marvell Armada AP806";
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compatible = "marvell,armada-ap806";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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gpio0 = &ap_gpio;
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spi0 = &spi0;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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ap806 {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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config-space@f0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x0 0x0 0xf0000000 0x1000000>;
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gic: interrupt-controller@210000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-controller;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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reg = <0x210000 0x10000>,
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<0x220000 0x20000>,
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<0x240000 0x20000>,
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<0x260000 0x20000>;
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gic_v2m0: v2m@280000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x280000 0x1000>;
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arm,msi-base-spi = <160>;
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arm,msi-num-spis = <32>;
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};
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gic_v2m1: v2m@290000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x290000 0x1000>;
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arm,msi-base-spi = <192>;
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arm,msi-num-spis = <32>;
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};
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gic_v2m2: v2m@2a0000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x2a0000 0x1000>;
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arm,msi-base-spi = <224>;
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arm,msi-num-spis = <32>;
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};
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gic_v2m3: v2m@2b0000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x2b0000 0x1000>;
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arm,msi-base-spi = <256>;
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arm,msi-num-spis = <32>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu {
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compatible = "arm,cortex-a72-pmu";
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interrupt-parent = <&pic>;
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interrupts = <17>;
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};
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odmi: odmi@300000 {
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compatible = "marvell,odmi-controller";
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interrupt-controller;
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msi-controller;
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marvell,odmi-frames = <4>;
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reg = <0x300000 0x4000>,
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<0x304000 0x4000>,
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<0x308000 0x4000>,
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<0x30C000 0x4000>;
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marvell,spi-base = <128>, <136>, <144>, <152>;
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};
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gicp: gicp@3f0040 {
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compatible = "marvell,ap806-gicp";
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reg = <0x3f0040 0x10>;
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marvell,spi-ranges = <64 64>, <288 64>;
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msi-controller;
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};
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pic: interrupt-controller@3f0100 {
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compatible = "marvell,armada-8k-pic";
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reg = <0x3f0100 0x10>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
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};
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xor@400000 {
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compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
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reg = <0x400000 0x1000>,
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<0x410000 0x1000>;
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msi-parent = <&gic_v2m0>;
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clocks = <&ap_clk 3>;
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dma-coherent;
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};
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xor@420000 {
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compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
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reg = <0x420000 0x1000>,
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<0x430000 0x1000>;
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msi-parent = <&gic_v2m0>;
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clocks = <&ap_clk 3>;
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dma-coherent;
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};
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xor@440000 {
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compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
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reg = <0x440000 0x1000>,
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<0x450000 0x1000>;
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msi-parent = <&gic_v2m0>;
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clocks = <&ap_clk 3>;
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dma-coherent;
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};
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xor@460000 {
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compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
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reg = <0x460000 0x1000>,
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<0x470000 0x1000>;
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msi-parent = <&gic_v2m0>;
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clocks = <&ap_clk 3>;
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dma-coherent;
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};
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spi0: spi@510600 {
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compatible = "marvell,armada-380-spi";
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reg = <0x510600 0x50>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ap_clk 3>;
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status = "disabled";
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};
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i2c0: i2c@511000 {
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compatible = "marvell,mv78230-i2c";
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reg = <0x511000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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timeout-ms = <1000>;
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clocks = <&ap_clk 3>;
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status = "disabled";
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};
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uart0: serial@512000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x512000 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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clocks = <&ap_clk 3>;
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status = "disabled";
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};
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uart1: serial@512100 {
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compatible = "snps,dw-apb-uart";
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reg = <0x512100 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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clocks = <&ap_clk 3>;
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status = "disabled";
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};
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watchdog: watchdog@610000 {
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compatible = "arm,sbsa-gwdt";
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reg = <0x610000 0x1000>, <0x600000 0x1000>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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};
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ap_sdhci0: sdhci@6e0000 {
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compatible = "marvell,armada-ap806-sdhci";
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reg = <0x6e0000 0x300>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "core";
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clocks = <&ap_clk 4>;
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dma-coherent;
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marvell,xenon-phy-slow-mode;
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status = "disabled";
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};
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ap_syscon: system-controller@6f4000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x6f4000 0x2000>;
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ap_clk: clock {
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compatible = "marvell,ap806-clock";
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#clock-cells = <1>;
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};
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ap_pinctrl: pinctrl {
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compatible = "marvell,ap806-pinctrl";
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uart0_pins: uart0-pins {
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marvell,pins = "mpp11", "mpp19";
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marvell,function = "uart0";
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};
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};
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ap_gpio: gpio@1040 {
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compatible = "marvell,armada-8k-gpio";
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offset = <0x1040>;
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ngpios = <20>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&ap_pinctrl 0 0 20>;
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};
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};
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ap_thermal: thermal@6f808c {
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compatible = "marvell,armada-ap806-thermal";
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reg = <0x6f808c 0x4>,
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<0x6f8084 0x8>;
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};
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};
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};
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};
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