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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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030d0178bd
ARM uses ll/sc primitives that do not imply barriers for all regular
atomic ops, therefore smp_mb__{before,after} need be a full barrier.
Since ARM doesn't use asm-generic/barrier.h include the required
definitions in its asm/barrier.h
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Link: http://lkml.kernel.org/n/tip-yijo7sglsl7uusbp13upcuvo@git.kernel.org
Cc: Albin Tonnerre <albin.tonnerre@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Chen Gang <gang.chen@asianux.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Nicolas Pitre <nico@linaro.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Victor Kamensky <victor.kamensky@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
87 lines
2.7 KiB
C
87 lines
2.7 KiB
C
#ifndef __ASM_BARRIER_H
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#define __ASM_BARRIER_H
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#ifndef __ASSEMBLY__
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#include <asm/outercache.h>
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#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
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#if __LINUX_ARM_ARCH__ >= 7 || \
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(__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
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#define sev() __asm__ __volatile__ ("sev" : : : "memory")
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#define wfe() __asm__ __volatile__ ("wfe" : : : "memory")
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#define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
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#endif
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#if __LINUX_ARM_ARCH__ >= 7
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#define isb(option) __asm__ __volatile__ ("isb " #option : : : "memory")
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#define dsb(option) __asm__ __volatile__ ("dsb " #option : : : "memory")
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#define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory")
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#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
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#define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
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: : "r" (0) : "memory")
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#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
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: : "r" (0) : "memory")
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#define dmb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
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: : "r" (0) : "memory")
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#elif defined(CONFIG_CPU_FA526)
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#define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
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: : "r" (0) : "memory")
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#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
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: : "r" (0) : "memory")
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#define dmb(x) __asm__ __volatile__ ("" : : : "memory")
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#else
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#define isb(x) __asm__ __volatile__ ("" : : : "memory")
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#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
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: : "r" (0) : "memory")
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#define dmb(x) __asm__ __volatile__ ("" : : : "memory")
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#endif
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#ifdef CONFIG_ARCH_HAS_BARRIERS
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#include <mach/barriers.h>
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#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
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#define mb() do { dsb(); outer_sync(); } while (0)
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#define rmb() dsb()
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#define wmb() do { dsb(st); outer_sync(); } while (0)
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#else
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#define mb() barrier()
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#define rmb() barrier()
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#define wmb() barrier()
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#endif
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#ifndef CONFIG_SMP
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#else
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#define smp_mb() dmb(ish)
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#define smp_rmb() smp_mb()
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#define smp_wmb() dmb(ishst)
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#endif
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#define smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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smp_mb(); \
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ACCESS_ONCE(*p) = (v); \
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} while (0)
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#define smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = ACCESS_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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smp_mb(); \
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___p1; \
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})
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#define read_barrier_depends() do { } while(0)
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#define smp_read_barrier_depends() do { } while(0)
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#define set_mb(var, value) do { var = value; smp_mb(); } while (0)
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#define smp_mb__before_atomic() smp_mb()
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#define smp_mb__after_atomic() smp_mb()
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#endif /* !__ASSEMBLY__ */
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#endif /* __ASM_BARRIER_H */
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