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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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00a9730e10
This patch adds cache and tlb sync codes for abiv1 & abiv2. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
26 lines
555 B
C
26 lines
555 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#ifndef __ASM_CSKY_TLB_H
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#define __ASM_CSKY_TLB_H
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#include <asm/cacheflush.h>
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#define tlb_start_vma(tlb, vma) \
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do { \
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if (!tlb->fullmm) \
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flush_cache_range(vma, vma->vm_start, vma->vm_end); \
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} while (0)
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#define tlb_end_vma(tlb, vma) \
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do { \
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if (!tlb->fullmm) \
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flush_tlb_range(vma, vma->vm_start, vma->vm_end); \
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} while (0)
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#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
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#include <asm-generic/tlb.h>
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#endif /* __ASM_CSKY_TLB_H */
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