mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
e9564df753
This patch adds files related to task_switch, sigcontext, signal, fpu context switch. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Eric W. Biederman <ebiederm@xmission.com>
151 lines
3.7 KiB
C
151 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#ifndef __ASM_CSKY_MMU_CONTEXT_H
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#define __ASM_CSKY_MMU_CONTEXT_H
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#include <asm-generic/mm_hooks.h>
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#include <asm/setup.h>
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#include <asm/page.h>
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#include <asm/cacheflush.h>
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#include <asm/tlbflush.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <abi/ckmmu.h>
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static inline void tlbmiss_handler_setup_pgd(unsigned long pgd, bool kernel)
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{
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pgd &= ~(1<<31);
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pgd += PHYS_OFFSET;
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pgd |= 1;
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setup_pgd(pgd, kernel);
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}
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#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
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tlbmiss_handler_setup_pgd((unsigned long)pgd, 0)
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#define TLBMISS_HANDLER_SETUP_PGD_KERNEL(pgd) \
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tlbmiss_handler_setup_pgd((unsigned long)pgd, 1)
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static inline unsigned long tlb_get_pgd(void)
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{
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return ((get_pgd()|(1<<31)) - PHYS_OFFSET) & ~1;
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}
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#define cpu_context(cpu, mm) ((mm)->context.asid[cpu])
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#define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK)
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#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
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#define ASID_FIRST_VERSION (1 << CONFIG_CPU_ASID_BITS)
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#define ASID_INC 0x1
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#define ASID_MASK (ASID_FIRST_VERSION - 1)
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#define ASID_VERSION_MASK ~ASID_MASK
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#define destroy_context(mm) do {} while (0)
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#define enter_lazy_tlb(mm, tsk) do {} while (0)
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#define deactivate_mm(tsk, mm) do {} while (0)
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/*
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* All unused by hardware upper bits will be considered
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* as a software asid extension.
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*/
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static inline void
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get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
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{
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unsigned long asid = asid_cache(cpu);
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asid += ASID_INC;
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if (!(asid & ASID_MASK)) {
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flush_tlb_all(); /* start new asid cycle */
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if (!asid) /* fix version if needed */
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asid = ASID_FIRST_VERSION;
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}
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cpu_context(cpu, mm) = asid_cache(cpu) = asid;
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}
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/*
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* Initialize the context related info for a new mm_struct
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* instance.
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*/
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static inline int
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init_new_context(struct task_struct *tsk, struct mm_struct *mm)
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{
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int i;
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for_each_online_cpu(i)
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cpu_context(i, mm) = 0;
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return 0;
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}
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static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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unsigned int cpu = smp_processor_id();
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unsigned long flags;
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local_irq_save(flags);
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/* Check if our ASID is of an older version and thus invalid */
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if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK)
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get_new_mmu_context(next, cpu);
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write_mmu_entryhi(cpu_asid(cpu, next));
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TLBMISS_HANDLER_SETUP_PGD(next->pgd);
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/*
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* Mark current->active_mm as not "active" anymore.
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* We don't want to mislead possible IPI tlb flush routines.
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*/
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cpumask_clear_cpu(cpu, mm_cpumask(prev));
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cpumask_set_cpu(cpu, mm_cpumask(next));
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local_irq_restore(flags);
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}
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/*
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* After we have set current->mm to a new value, this activates
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* the context for the new mm so we see the new mappings.
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*/
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static inline void
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activate_mm(struct mm_struct *prev, struct mm_struct *next)
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{
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unsigned long flags;
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int cpu = smp_processor_id();
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local_irq_save(flags);
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/* Unconditionally get a new ASID. */
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get_new_mmu_context(next, cpu);
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write_mmu_entryhi(cpu_asid(cpu, next));
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TLBMISS_HANDLER_SETUP_PGD(next->pgd);
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/* mark mmu ownership change */
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cpumask_clear_cpu(cpu, mm_cpumask(prev));
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cpumask_set_cpu(cpu, mm_cpumask(next));
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local_irq_restore(flags);
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}
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/*
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* If mm is currently active_mm, we can't really drop it. Instead,
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* we will get a new one for it.
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*/
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static inline void
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drop_mmu_context(struct mm_struct *mm, unsigned int cpu)
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{
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unsigned long flags;
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local_irq_save(flags);
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if (cpumask_test_cpu(cpu, mm_cpumask(mm))) {
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get_new_mmu_context(mm, cpu);
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write_mmu_entryhi(cpu_asid(cpu, mm));
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} else {
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/* will get a new context next time */
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cpu_context(cpu, mm) = 0;
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}
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local_irq_restore(flags);
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}
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#endif /* __ASM_CSKY_MMU_CONTEXT_H */
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