mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 09:24:37 +07:00
29ae0952e8
Add the pinctrl driver for Meson-G12A SoC which share the similar IP as the previous Meson-AXG SoC, both use same pinmux ops (register layout). A new driver is needed here due to the differences in the pins. Starting from Meson-AXG SoC, the pinctrl controller block use 4 continues register bits to specific the pin mux function, while comparing to old generation SoC which using variable length register bits for the pin mux definition. The new design greatly simplify the software model. For the detail example, one 32bit register can be divided into 8 parts, each has 4 bits whose value start from 0 - 7, each can describe one pin, the value 0 is always devoted to GPIO function, while 1 - 7 devoted to the mux pin function. Please note, the GPIOE is actually located at AO (always on) bank. Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
10 lines
491 B
Makefile
10 lines
491 B
Makefile
obj-$(CONFIG_PINCTRL_MESON) += pinctrl-meson.o
|
|
obj-$(CONFIG_PINCTRL_MESON8_PMX) += pinctrl-meson8-pmx.o
|
|
obj-$(CONFIG_PINCTRL_MESON8) += pinctrl-meson8.o
|
|
obj-$(CONFIG_PINCTRL_MESON8B) += pinctrl-meson8b.o
|
|
obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o
|
|
obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o
|
|
obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o
|
|
obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o
|
|
obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o
|