Linus Torvalds 6a0e20cd8c First set of RISC-V updates for v5.5-rc1 ... New features: - SECCOMP support - nommu support - SBI-less system support - M-Mode support - TLB flush optimizations Other improvements: - Pass the complete RISC-V ISA string supported by the CPU cores to userspace, rather than redacting parts of it in the kernel - Add platform DMA IP block data to the HiFive Unleashed board DT file - Add Makefile support for BZ2, LZ4, LZMA, LZO kernel image compression formats, in line with other architectures Cleanups: - Remove unnecessary PTE_PARENT_SIZE macro - Standardize include guard naming across arch/riscv -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEElRDoIDdEz9/svf2Kx4+xDQu9KksFAl3dkMcACgkQx4+xDQu9 KksoQA/+MZdtMrSe+j5yep7ZO803ivdS5tPCjNI06An2Ps8OJmJKoU8zSCIbygfM xIQ8R5KVLjd1DTW3SKNrL3bUsH0PdwGHKj69z0gMA01kGBe5CfJEzHw03U4It++t xaPAYJje99xtdEzZMro/Z+/Gsz/XM5SDZmY4i6quSlHOmL0HP6zftk3jPvxO+XtD 7unQJSHuZElqs984OmR+6DUTiaIlJ4P+/xxlFydswq19/tDNCXpukLhMHkOND3W+ 3dBHAp9U18dz2I8lD3xlppVbvgCnud7z+xa+XY1Q/BluoYIEe6714S+9lr8TCdTP 43wL9hSvbDPyaydnmKU7VqwdcWrbVQkA7H3GtxeiUZYvyDdidk9sARqg0n6uoedw 48uRfeI0jCQXh6XdFNMCqNgYPpcpHY3isMKVCi2U6TT0fNdUUC3f62qsOIP0vQXh 4hDys5JzIoBKv8nz/ap+1xzUluBt6FGmySPlTbd8ryn2m2Yd0EsHjywcEGRJMrlM KcOYgLAKcr9rRF4ap/NqQy74AvC+pOcDVeUHPD0WXYDRQn6L0wbp8YElzRf8W1BC b7osrRSNLfzC2LsEUEK+qYHrT4+cuWBbkuobAEHMY/OnLW1OKEifZQIdknAE1/yg n2qy4DuA6qta+Q1GiH8OOt9AEYHPw+SDP3+qFaJK5ZZMb3v565A= =nbwY -----END PGP SIGNATURE----- Merge tag 'riscv/for-v5.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Paul Walmsley: "New features: - SECCOMP support - nommu support - SBI-less system support - M-Mode support - TLB flush optimizations Other improvements: - Pass the complete RISC-V ISA string supported by the CPU cores to userspace, rather than redacting parts of it in the kernel - Add platform DMA IP block data to the HiFive Unleashed board DT file - Add Makefile support for BZ2, LZ4, LZMA, LZO kernel image compression formats, in line with other architectures Cleanups: - Remove unnecessary PTE_PARENT_SIZE macro - Standardize include guard naming across arch/riscv" * tag 'riscv/for-v5.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (22 commits) riscv: provide a flat image loader riscv: add nommu support riscv: clear the instruction cache and all registers when booting riscv: read the hart ID from mhartid on boot riscv: provide native clint access for M-mode riscv: dts: add support for PDMA device of HiFive Unleashed Rev A00 riscv: add support for MMIO access to the timer registers riscv: implement remote sfence.i using IPIs riscv: cleanup the default power off implementation riscv: poison SBI calls for M-mode riscv: don't allow selecting SBI based drivers for M-mode RISC-V: Add multiple compression image format. riscv: clean up the macro format in each header file riscv: Use PMD_SIZE to replace PTE_PARENT_SIZE riscv: abstract out CSR names for supervisor vs machine mode riscv: separate MMIO functions into their own header file riscv: enter WFI in default_power_off() if SBI does not shutdown RISC-V: Issue a tlb page flush if possible RISC-V: Issue a local tlbflush if possible. RISC-V: Do not invoke SBI call if cpumask is empty ...		2019-11-27 11:27:59 -08:00
..
acpi_pm.c
arc_timer.c
arm_arch_timer.c
arm_global_timer.c
armv7m_systick.c
asm9260_timer.c
bcm2835_timer.c
bcm_kona_timer.c
clksrc_st_lpc.c
clksrc-dbx500-prcmu.c
clps711x-timer.c
dummy_timer.c
dw_apb_timer_of.c
dw_apb_timer.c
em_sti.c
exynos_mct.c
h8300_timer8.c
h8300_timer16.c
h8300_tpu.c
hyperv_timer.c	x86/hyperv: Initialize clockevents earlier in CPU onlining	2019-11-15 10:33:49 +01:00
i8253.c
ingenic-timer.c
jcore-pit.c
Kconfig
Makefile
mips-gic-timer.c
mmio.c
mps2-timer.c
mxs_timer.c
nomadik-mtu.c
numachip.c
renesas-ostm.c
samsung_pwm_timer.c	clocksource: samsung_pwm_timer: Use pr_warn instead of pr_warning	2019-10-18 15:00:20 +02:00
scx200_hrt.c
sh_cmt.c	sh: add the sh_ prefix to early platform symbols	2019-10-07 13:50:48 +02:00
sh_mtu2.c	Driver core patches for 5.5-rc1	2019-11-27 11:06:20 -08:00
sh_tmu.c	sh: add the sh_ prefix to early platform symbols	2019-10-07 13:50:48 +02:00
timer-armada-370-xp.c
timer-atcpit100.c
timer-atlas7.c
timer-atmel-pit.c
timer-atmel-st.c
timer-atmel-tcb.c
timer-cadence-ttc.c
timer-cs5535.c
timer-davinci.c
timer-digicolor.c
timer-efm32.c
timer-fsl-ftm.c
timer-fttmr010.c
timer-gx6605s.c
timer-imx-gpt.c
timer-imx-sysctr.c
timer-imx-tpm.c
timer-integrator-ap.c
timer-ixp4xx.c
timer-keystone.c
timer-lpc32xx.c
timer-mediatek.c	clocksource/drivers/mediatek: Fix error handling	2019-10-16 17:04:50 +02:00
timer-meson6.c
timer-milbeaut.c
timer-mp-csky.c
timer-npcm7xx.c
timer-nps.c
timer-of.c
timer-of.h
timer-orion.c
timer-owl.c
timer-oxnas-rps.c
timer-pistachio.c
timer-prima2.c
timer-probe.c
timer-pxa.c
timer-qcom.c
timer-rda.c
timer-riscv.c	riscv: add support for MMIO access to the timer registers	2019-11-13 14:10:40 -08:00
timer-rockchip.c
timer-sp804.c
timer-sp.h
timer-sprd.c
timer-stm32.c
timer-sun4i.c
timer-sun5i.c
timer-tango-xtal.c
timer-tegra.c
timer-ti-32k.c
timer-ti-dm.c
timer-u300.c
timer-versatile.c
timer-vf-pit.c
timer-vt8500.c
timer-zevio.c