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db60d8da8f
edma header defines DMA_COMPLETE, this causes issues as commit adfedd9a32 move
DMA_SUCCESS to DMA_COMPLETE. edma should properly namespace its defines and
needs a future fix
Reported-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
186 lines
5.5 KiB
C
186 lines
5.5 KiB
C
/*
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* TI EDMA definitions
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*
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* Copyright (C) 2006-2013 Texas Instruments.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/*
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* This EDMA3 programming framework exposes two basic kinds of resource:
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*
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* Channel Triggers transfers, usually from a hardware event but
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* also manually or by "chaining" from DMA completions.
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* Each channel is coupled to a Parameter RAM (PaRAM) slot.
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*
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* Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
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* "set"), source and destination addresses, a link to a
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* next PaRAM slot (if any), options for the transfer, and
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* instructions for updating those addresses. There are
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* more than twice as many slots as event channels.
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*
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* Each PaRAM set describes a sequence of transfers, either for one large
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* buffer or for several discontiguous smaller buffers. An EDMA transfer
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* is driven only from a channel, which performs the transfers specified
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* in its PaRAM slot until there are no more transfers. When that last
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* transfer completes, the "link" field may be used to reload the channel's
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* PaRAM slot with a new transfer descriptor.
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*
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* The EDMA Channel Controller (CC) maps requests from channels into physical
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* Transfer Controller (TC) requests when the channel triggers (by hardware
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* or software events, or by chaining). The two physical DMA channels provided
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* by the TCs are thus shared by many logical channels.
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*
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* DaVinci hardware also has a "QDMA" mechanism which is not currently
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* supported through this interface. (DSP firmware uses it though.)
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*/
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#ifndef EDMA_H_
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#define EDMA_H_
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/* PaRAM slots are laid out like this */
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struct edmacc_param {
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unsigned int opt;
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unsigned int src;
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unsigned int a_b_cnt;
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unsigned int dst;
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unsigned int src_dst_bidx;
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unsigned int link_bcntrld;
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unsigned int src_dst_cidx;
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unsigned int ccnt;
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};
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/* fields in edmacc_param.opt */
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#define SAM BIT(0)
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#define DAM BIT(1)
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#define SYNCDIM BIT(2)
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#define STATIC BIT(3)
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#define EDMA_FWID (0x07 << 8)
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#define TCCMODE BIT(11)
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#define EDMA_TCC(t) ((t) << 12)
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#define TCINTEN BIT(20)
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#define ITCINTEN BIT(21)
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#define TCCHEN BIT(22)
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#define ITCCHEN BIT(23)
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/*ch_status paramater of callback function possible values*/
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#define EDMA_DMA_COMPLETE 1
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#define EDMA_DMA_CC_ERROR 2
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#define EDMA_DMA_TC1_ERROR 3
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#define EDMA_DMA_TC2_ERROR 4
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enum address_mode {
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INCR = 0,
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FIFO = 1
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};
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enum fifo_width {
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W8BIT = 0,
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W16BIT = 1,
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W32BIT = 2,
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W64BIT = 3,
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W128BIT = 4,
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W256BIT = 5
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};
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enum dma_event_q {
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EVENTQ_0 = 0,
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EVENTQ_1 = 1,
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EVENTQ_2 = 2,
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EVENTQ_3 = 3,
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EVENTQ_DEFAULT = -1
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};
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enum sync_dimension {
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ASYNC = 0,
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ABSYNC = 1
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};
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#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan))
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#define EDMA_CTLR(i) ((i) >> 16)
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#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
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#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
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#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
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#define EDMA_CONT_PARAMS_ANY 1001
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#define EDMA_CONT_PARAMS_FIXED_EXACT 1002
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#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
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#define EDMA_MAX_CC 2
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/* alloc/free DMA channels and their dedicated parameter RAM slots */
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int edma_alloc_channel(int channel,
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void (*callback)(unsigned channel, u16 ch_status, void *data),
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void *data, enum dma_event_q);
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void edma_free_channel(unsigned channel);
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/* alloc/free parameter RAM slots */
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int edma_alloc_slot(unsigned ctlr, int slot);
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void edma_free_slot(unsigned slot);
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/* alloc/free a set of contiguous parameter RAM slots */
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int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
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int edma_free_cont_slots(unsigned slot, int count);
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/* calls that operate on part of a parameter RAM slot */
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void edma_set_src(unsigned slot, dma_addr_t src_port,
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enum address_mode mode, enum fifo_width);
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void edma_set_dest(unsigned slot, dma_addr_t dest_port,
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enum address_mode mode, enum fifo_width);
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void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst);
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void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
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void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
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void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
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u16 bcnt_rld, enum sync_dimension sync_mode);
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void edma_link(unsigned from, unsigned to);
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void edma_unlink(unsigned from);
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/* calls that operate on an entire parameter RAM slot */
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void edma_write_slot(unsigned slot, const struct edmacc_param *params);
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void edma_read_slot(unsigned slot, struct edmacc_param *params);
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/* channel control operations */
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int edma_start(unsigned channel);
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void edma_stop(unsigned channel);
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void edma_clean_channel(unsigned channel);
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void edma_clear_event(unsigned channel);
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void edma_pause(unsigned channel);
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void edma_resume(unsigned channel);
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struct edma_rsv_info {
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const s16 (*rsv_chans)[2];
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const s16 (*rsv_slots)[2];
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};
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/* platform_data for EDMA driver */
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struct edma_soc_info {
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/* how many dma resources of each type */
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unsigned n_channel;
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unsigned n_region;
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unsigned n_slot;
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unsigned n_tc;
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unsigned n_cc;
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/*
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* Default queue is expected to be a low-priority queue.
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* This way, long transfers on the default queue started
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* by the codec engine will not cause audio defects.
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*/
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enum dma_event_q default_queue;
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/* Resource reservation for other cores */
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struct edma_rsv_info *rsv;
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s8 (*queue_tc_mapping)[2];
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s8 (*queue_priority_mapping)[2];
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const s16 (*xbar_chans)[2];
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};
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int edma_trigger_channel(unsigned);
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#endif
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