mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-06 04:56:41 +07:00
0252937a87
The default for the Xen hypervisor is to not enable VPMU in order to avoid security issues. In this case the Linux kernel will issue the message "Could not initialize VPMU for cpu 0, error -95" which looks more like an error than a normal state. Change the message to something less scary in case the hypervisor returns EOPNOTSUPP or ENOSYS when trying to activate VPMU. Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: David Vrabel <david.vrabel@citrix.com>
574 lines
13 KiB
C
574 lines
13 KiB
C
#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <asm/xen/hypercall.h>
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#include <xen/page.h>
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#include <xen/interface/xen.h>
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#include <xen/interface/vcpu.h>
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#include <xen/interface/xenpmu.h>
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#include "xen-ops.h"
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#include "pmu.h"
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/* x86_pmu.handle_irq definition */
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#include "../events/perf_event.h"
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#define XENPMU_IRQ_PROCESSING 1
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struct xenpmu {
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/* Shared page between hypervisor and domain */
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struct xen_pmu_data *xenpmu_data;
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uint8_t flags;
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};
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static DEFINE_PER_CPU(struct xenpmu, xenpmu_shared);
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#define get_xenpmu_data() (this_cpu_ptr(&xenpmu_shared)->xenpmu_data)
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#define get_xenpmu_flags() (this_cpu_ptr(&xenpmu_shared)->flags)
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/* Macro for computing address of a PMU MSR bank */
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#define field_offset(ctxt, field) ((void *)((uintptr_t)ctxt + \
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(uintptr_t)ctxt->field))
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/* AMD PMU */
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#define F15H_NUM_COUNTERS 6
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#define F10H_NUM_COUNTERS 4
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static __read_mostly uint32_t amd_counters_base;
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static __read_mostly uint32_t amd_ctrls_base;
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static __read_mostly int amd_msr_step;
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static __read_mostly int k7_counters_mirrored;
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static __read_mostly int amd_num_counters;
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/* Intel PMU */
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#define MSR_TYPE_COUNTER 0
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#define MSR_TYPE_CTRL 1
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#define MSR_TYPE_GLOBAL 2
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#define MSR_TYPE_ARCH_COUNTER 3
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#define MSR_TYPE_ARCH_CTRL 4
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/* Number of general pmu registers (CPUID.EAX[0xa].EAX[8..15]) */
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#define PMU_GENERAL_NR_SHIFT 8
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#define PMU_GENERAL_NR_BITS 8
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#define PMU_GENERAL_NR_MASK (((1 << PMU_GENERAL_NR_BITS) - 1) \
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<< PMU_GENERAL_NR_SHIFT)
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/* Number of fixed pmu registers (CPUID.EDX[0xa].EDX[0..4]) */
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#define PMU_FIXED_NR_SHIFT 0
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#define PMU_FIXED_NR_BITS 5
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#define PMU_FIXED_NR_MASK (((1 << PMU_FIXED_NR_BITS) - 1) \
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<< PMU_FIXED_NR_SHIFT)
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/* Alias registers (0x4c1) for full-width writes to PMCs */
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#define MSR_PMC_ALIAS_MASK (~(MSR_IA32_PERFCTR0 ^ MSR_IA32_PMC0))
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#define INTEL_PMC_TYPE_SHIFT 30
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static __read_mostly int intel_num_arch_counters, intel_num_fixed_counters;
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static void xen_pmu_arch_init(void)
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{
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if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
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switch (boot_cpu_data.x86) {
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case 0x15:
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amd_num_counters = F15H_NUM_COUNTERS;
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amd_counters_base = MSR_F15H_PERF_CTR;
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amd_ctrls_base = MSR_F15H_PERF_CTL;
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amd_msr_step = 2;
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k7_counters_mirrored = 1;
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break;
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case 0x10:
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case 0x12:
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case 0x14:
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case 0x16:
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default:
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amd_num_counters = F10H_NUM_COUNTERS;
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amd_counters_base = MSR_K7_PERFCTR0;
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amd_ctrls_base = MSR_K7_EVNTSEL0;
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amd_msr_step = 1;
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k7_counters_mirrored = 0;
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break;
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}
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} else {
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uint32_t eax, ebx, ecx, edx;
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cpuid(0xa, &eax, &ebx, &ecx, &edx);
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intel_num_arch_counters = (eax & PMU_GENERAL_NR_MASK) >>
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PMU_GENERAL_NR_SHIFT;
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intel_num_fixed_counters = (edx & PMU_FIXED_NR_MASK) >>
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PMU_FIXED_NR_SHIFT;
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}
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}
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static inline uint32_t get_fam15h_addr(u32 addr)
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{
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switch (addr) {
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case MSR_K7_PERFCTR0:
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case MSR_K7_PERFCTR1:
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case MSR_K7_PERFCTR2:
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case MSR_K7_PERFCTR3:
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return MSR_F15H_PERF_CTR + (addr - MSR_K7_PERFCTR0);
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case MSR_K7_EVNTSEL0:
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case MSR_K7_EVNTSEL1:
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case MSR_K7_EVNTSEL2:
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case MSR_K7_EVNTSEL3:
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return MSR_F15H_PERF_CTL + (addr - MSR_K7_EVNTSEL0);
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default:
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break;
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}
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return addr;
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}
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static inline bool is_amd_pmu_msr(unsigned int msr)
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{
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if ((msr >= MSR_F15H_PERF_CTL &&
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msr < MSR_F15H_PERF_CTR + (amd_num_counters * 2)) ||
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(msr >= MSR_K7_EVNTSEL0 &&
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msr < MSR_K7_PERFCTR0 + amd_num_counters))
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return true;
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return false;
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}
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static int is_intel_pmu_msr(u32 msr_index, int *type, int *index)
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{
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u32 msr_index_pmc;
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switch (msr_index) {
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case MSR_CORE_PERF_FIXED_CTR_CTRL:
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case MSR_IA32_DS_AREA:
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case MSR_IA32_PEBS_ENABLE:
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*type = MSR_TYPE_CTRL;
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return true;
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case MSR_CORE_PERF_GLOBAL_CTRL:
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case MSR_CORE_PERF_GLOBAL_STATUS:
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case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
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*type = MSR_TYPE_GLOBAL;
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return true;
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default:
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if ((msr_index >= MSR_CORE_PERF_FIXED_CTR0) &&
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(msr_index < MSR_CORE_PERF_FIXED_CTR0 +
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intel_num_fixed_counters)) {
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*index = msr_index - MSR_CORE_PERF_FIXED_CTR0;
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*type = MSR_TYPE_COUNTER;
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return true;
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}
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if ((msr_index >= MSR_P6_EVNTSEL0) &&
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(msr_index < MSR_P6_EVNTSEL0 + intel_num_arch_counters)) {
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*index = msr_index - MSR_P6_EVNTSEL0;
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*type = MSR_TYPE_ARCH_CTRL;
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return true;
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}
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msr_index_pmc = msr_index & MSR_PMC_ALIAS_MASK;
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if ((msr_index_pmc >= MSR_IA32_PERFCTR0) &&
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(msr_index_pmc < MSR_IA32_PERFCTR0 +
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intel_num_arch_counters)) {
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*type = MSR_TYPE_ARCH_COUNTER;
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*index = msr_index_pmc - MSR_IA32_PERFCTR0;
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return true;
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}
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return false;
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}
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}
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static bool xen_intel_pmu_emulate(unsigned int msr, u64 *val, int type,
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int index, bool is_read)
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{
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uint64_t *reg = NULL;
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struct xen_pmu_intel_ctxt *ctxt;
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uint64_t *fix_counters;
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struct xen_pmu_cntr_pair *arch_cntr_pair;
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struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
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uint8_t xenpmu_flags = get_xenpmu_flags();
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if (!xenpmu_data || !(xenpmu_flags & XENPMU_IRQ_PROCESSING))
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return false;
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ctxt = &xenpmu_data->pmu.c.intel;
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switch (msr) {
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case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
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reg = &ctxt->global_ovf_ctrl;
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break;
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case MSR_CORE_PERF_GLOBAL_STATUS:
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reg = &ctxt->global_status;
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break;
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case MSR_CORE_PERF_GLOBAL_CTRL:
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reg = &ctxt->global_ctrl;
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break;
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case MSR_CORE_PERF_FIXED_CTR_CTRL:
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reg = &ctxt->fixed_ctrl;
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break;
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default:
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switch (type) {
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case MSR_TYPE_COUNTER:
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fix_counters = field_offset(ctxt, fixed_counters);
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reg = &fix_counters[index];
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break;
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case MSR_TYPE_ARCH_COUNTER:
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arch_cntr_pair = field_offset(ctxt, arch_counters);
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reg = &arch_cntr_pair[index].counter;
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break;
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case MSR_TYPE_ARCH_CTRL:
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arch_cntr_pair = field_offset(ctxt, arch_counters);
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reg = &arch_cntr_pair[index].control;
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break;
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default:
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return false;
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}
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}
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if (reg) {
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if (is_read)
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*val = *reg;
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else {
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*reg = *val;
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if (msr == MSR_CORE_PERF_GLOBAL_OVF_CTRL)
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ctxt->global_status &= (~(*val));
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}
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return true;
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}
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return false;
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}
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static bool xen_amd_pmu_emulate(unsigned int msr, u64 *val, bool is_read)
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{
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uint64_t *reg = NULL;
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int i, off = 0;
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struct xen_pmu_amd_ctxt *ctxt;
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uint64_t *counter_regs, *ctrl_regs;
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struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
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uint8_t xenpmu_flags = get_xenpmu_flags();
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if (!xenpmu_data || !(xenpmu_flags & XENPMU_IRQ_PROCESSING))
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return false;
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if (k7_counters_mirrored &&
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((msr >= MSR_K7_EVNTSEL0) && (msr <= MSR_K7_PERFCTR3)))
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msr = get_fam15h_addr(msr);
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ctxt = &xenpmu_data->pmu.c.amd;
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for (i = 0; i < amd_num_counters; i++) {
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if (msr == amd_ctrls_base + off) {
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ctrl_regs = field_offset(ctxt, ctrls);
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reg = &ctrl_regs[i];
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break;
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} else if (msr == amd_counters_base + off) {
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counter_regs = field_offset(ctxt, counters);
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reg = &counter_regs[i];
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break;
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}
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off += amd_msr_step;
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}
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if (reg) {
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if (is_read)
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*val = *reg;
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else
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*reg = *val;
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return true;
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}
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return false;
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}
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bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err)
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{
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if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
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if (is_amd_pmu_msr(msr)) {
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if (!xen_amd_pmu_emulate(msr, val, 1))
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*val = native_read_msr_safe(msr, err);
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return true;
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}
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} else {
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int type, index;
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if (is_intel_pmu_msr(msr, &type, &index)) {
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if (!xen_intel_pmu_emulate(msr, val, type, index, 1))
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*val = native_read_msr_safe(msr, err);
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return true;
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}
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}
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return false;
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}
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bool pmu_msr_write(unsigned int msr, uint32_t low, uint32_t high, int *err)
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{
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uint64_t val = ((uint64_t)high << 32) | low;
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if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
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if (is_amd_pmu_msr(msr)) {
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if (!xen_amd_pmu_emulate(msr, &val, 0))
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*err = native_write_msr_safe(msr, low, high);
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return true;
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}
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} else {
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int type, index;
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if (is_intel_pmu_msr(msr, &type, &index)) {
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if (!xen_intel_pmu_emulate(msr, &val, type, index, 0))
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*err = native_write_msr_safe(msr, low, high);
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return true;
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}
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}
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return false;
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}
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static unsigned long long xen_amd_read_pmc(int counter)
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{
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struct xen_pmu_amd_ctxt *ctxt;
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uint64_t *counter_regs;
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struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
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uint8_t xenpmu_flags = get_xenpmu_flags();
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if (!xenpmu_data || !(xenpmu_flags & XENPMU_IRQ_PROCESSING)) {
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uint32_t msr;
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int err;
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msr = amd_counters_base + (counter * amd_msr_step);
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return native_read_msr_safe(msr, &err);
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}
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ctxt = &xenpmu_data->pmu.c.amd;
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counter_regs = field_offset(ctxt, counters);
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return counter_regs[counter];
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}
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static unsigned long long xen_intel_read_pmc(int counter)
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{
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struct xen_pmu_intel_ctxt *ctxt;
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uint64_t *fixed_counters;
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struct xen_pmu_cntr_pair *arch_cntr_pair;
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struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
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uint8_t xenpmu_flags = get_xenpmu_flags();
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if (!xenpmu_data || !(xenpmu_flags & XENPMU_IRQ_PROCESSING)) {
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uint32_t msr;
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int err;
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if (counter & (1 << INTEL_PMC_TYPE_SHIFT))
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msr = MSR_CORE_PERF_FIXED_CTR0 + (counter & 0xffff);
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else
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msr = MSR_IA32_PERFCTR0 + counter;
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return native_read_msr_safe(msr, &err);
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}
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ctxt = &xenpmu_data->pmu.c.intel;
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if (counter & (1 << INTEL_PMC_TYPE_SHIFT)) {
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fixed_counters = field_offset(ctxt, fixed_counters);
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return fixed_counters[counter & 0xffff];
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}
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arch_cntr_pair = field_offset(ctxt, arch_counters);
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return arch_cntr_pair[counter].counter;
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}
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unsigned long long xen_read_pmc(int counter)
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{
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if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
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return xen_amd_read_pmc(counter);
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else
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return xen_intel_read_pmc(counter);
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}
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int pmu_apic_update(uint32_t val)
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{
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int ret;
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struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
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if (!xenpmu_data) {
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pr_warn_once("%s: pmudata not initialized\n", __func__);
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return -EINVAL;
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}
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xenpmu_data->pmu.l.lapic_lvtpc = val;
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if (get_xenpmu_flags() & XENPMU_IRQ_PROCESSING)
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return 0;
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ret = HYPERVISOR_xenpmu_op(XENPMU_lvtpc_set, NULL);
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return ret;
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}
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/* perf callbacks */
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static int xen_is_in_guest(void)
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{
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const struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
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if (!xenpmu_data) {
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pr_warn_once("%s: pmudata not initialized\n", __func__);
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return 0;
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}
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if (!xen_initial_domain() || (xenpmu_data->domain_id >= DOMID_SELF))
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return 0;
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return 1;
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}
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static int xen_is_user_mode(void)
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{
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const struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
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if (!xenpmu_data) {
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pr_warn_once("%s: pmudata not initialized\n", __func__);
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return 0;
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}
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if (xenpmu_data->pmu.pmu_flags & PMU_SAMPLE_PV)
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return (xenpmu_data->pmu.pmu_flags & PMU_SAMPLE_USER);
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else
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return !!(xenpmu_data->pmu.r.regs.cpl & 3);
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}
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static unsigned long xen_get_guest_ip(void)
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{
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const struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
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if (!xenpmu_data) {
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pr_warn_once("%s: pmudata not initialized\n", __func__);
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return 0;
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}
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return xenpmu_data->pmu.r.regs.ip;
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}
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static struct perf_guest_info_callbacks xen_guest_cbs = {
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.is_in_guest = xen_is_in_guest,
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.is_user_mode = xen_is_user_mode,
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.get_guest_ip = xen_get_guest_ip,
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};
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/* Convert registers from Xen's format to Linux' */
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static void xen_convert_regs(const struct xen_pmu_regs *xen_regs,
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struct pt_regs *regs, uint64_t pmu_flags)
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{
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regs->ip = xen_regs->ip;
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regs->cs = xen_regs->cs;
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regs->sp = xen_regs->sp;
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if (pmu_flags & PMU_SAMPLE_PV) {
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if (pmu_flags & PMU_SAMPLE_USER)
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regs->cs |= 3;
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else
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regs->cs &= ~3;
|
|
} else {
|
|
if (xen_regs->cpl)
|
|
regs->cs |= 3;
|
|
else
|
|
regs->cs &= ~3;
|
|
}
|
|
}
|
|
|
|
irqreturn_t xen_pmu_irq_handler(int irq, void *dev_id)
|
|
{
|
|
int err, ret = IRQ_NONE;
|
|
struct pt_regs regs;
|
|
const struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
|
|
uint8_t xenpmu_flags = get_xenpmu_flags();
|
|
|
|
if (!xenpmu_data) {
|
|
pr_warn_once("%s: pmudata not initialized\n", __func__);
|
|
return ret;
|
|
}
|
|
|
|
this_cpu_ptr(&xenpmu_shared)->flags =
|
|
xenpmu_flags | XENPMU_IRQ_PROCESSING;
|
|
xen_convert_regs(&xenpmu_data->pmu.r.regs, ®s,
|
|
xenpmu_data->pmu.pmu_flags);
|
|
if (x86_pmu.handle_irq(®s))
|
|
ret = IRQ_HANDLED;
|
|
|
|
/* Write out cached context to HW */
|
|
err = HYPERVISOR_xenpmu_op(XENPMU_flush, NULL);
|
|
this_cpu_ptr(&xenpmu_shared)->flags = xenpmu_flags;
|
|
if (err) {
|
|
pr_warn_once("%s: failed hypercall, err: %d\n", __func__, err);
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
bool is_xen_pmu(int cpu)
|
|
{
|
|
return (get_xenpmu_data() != NULL);
|
|
}
|
|
|
|
void xen_pmu_init(int cpu)
|
|
{
|
|
int err;
|
|
struct xen_pmu_params xp;
|
|
unsigned long pfn;
|
|
struct xen_pmu_data *xenpmu_data;
|
|
|
|
BUILD_BUG_ON(sizeof(struct xen_pmu_data) > PAGE_SIZE);
|
|
|
|
if (xen_hvm_domain())
|
|
return;
|
|
|
|
xenpmu_data = (struct xen_pmu_data *)get_zeroed_page(GFP_KERNEL);
|
|
if (!xenpmu_data) {
|
|
pr_err("VPMU init: No memory\n");
|
|
return;
|
|
}
|
|
pfn = virt_to_pfn(xenpmu_data);
|
|
|
|
xp.val = pfn_to_mfn(pfn);
|
|
xp.vcpu = cpu;
|
|
xp.version.maj = XENPMU_VER_MAJ;
|
|
xp.version.min = XENPMU_VER_MIN;
|
|
err = HYPERVISOR_xenpmu_op(XENPMU_init, &xp);
|
|
if (err)
|
|
goto fail;
|
|
|
|
per_cpu(xenpmu_shared, cpu).xenpmu_data = xenpmu_data;
|
|
per_cpu(xenpmu_shared, cpu).flags = 0;
|
|
|
|
if (cpu == 0) {
|
|
perf_register_guest_info_callbacks(&xen_guest_cbs);
|
|
xen_pmu_arch_init();
|
|
}
|
|
|
|
return;
|
|
|
|
fail:
|
|
if (err == -EOPNOTSUPP || err == -ENOSYS)
|
|
pr_info_once("VPMU disabled by hypervisor.\n");
|
|
else
|
|
pr_info_once("Could not initialize VPMU for cpu %d, error %d\n",
|
|
cpu, err);
|
|
free_pages((unsigned long)xenpmu_data, 0);
|
|
}
|
|
|
|
void xen_pmu_finish(int cpu)
|
|
{
|
|
struct xen_pmu_params xp;
|
|
|
|
if (xen_hvm_domain())
|
|
return;
|
|
|
|
xp.vcpu = cpu;
|
|
xp.version.maj = XENPMU_VER_MAJ;
|
|
xp.version.min = XENPMU_VER_MIN;
|
|
|
|
(void)HYPERVISOR_xenpmu_op(XENPMU_finish, &xp);
|
|
|
|
free_pages((unsigned long)per_cpu(xenpmu_shared, cpu).xenpmu_data, 0);
|
|
per_cpu(xenpmu_shared, cpu).xenpmu_data = NULL;
|
|
}
|