mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-16 10:37:01 +07:00
197858b685
stm32mp1 RCC IP 1 has a reset SET register and a reset CLEAR register. Writing '0' on reset SET register has no effect Writing '1' on reset SET register activates the reset of the corresponding peripheral Writing '0' on reset CLEAR register has no effect Writing '1' on reset CLEAR register releases the reset of the corresponding peripheral See Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
25 lines
950 B
Makefile
25 lines
950 B
Makefile
# SPDX-License-Identifier: GPL-2.0
|
|
obj-y += core.o
|
|
obj-y += hisilicon/
|
|
obj-$(CONFIG_ARCH_STI) += sti/
|
|
obj-$(CONFIG_ARCH_TEGRA) += tegra/
|
|
obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
|
|
obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
|
|
obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
|
|
obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
|
|
obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
|
|
obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
|
|
obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
|
|
obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
|
|
obj-$(CONFIG_RESET_MESON) += reset-meson.o
|
|
obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
|
|
obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
|
|
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
|
|
obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
|
|
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
|
|
obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
|
|
obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
|
|
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
|
|
obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o
|
|
|