mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-16 23:26:42 +07:00
9798f5178f
Core changes: - Disallow open drain and open source flags to be set simultaneously. This doesn't make electrical sense, and would the hardware actually respond to this setting, the result would be short circuit. - ACPI GPIO has a new core infrastructure for handling quirks. The quirks are there to deal with broken ACPI tables centrally instead of pushing the work to individual drivers. In the world of BIOS writers, the ACPI tables are perfect. Until they find a mistake in it. When such a mistake is found, we can patch it with a quirk. It should never happen, the problem is that it happens. So we accomodate for it. - Several documentation updates. - Revert the patch setting up initial direction state from reading the device. This was causing bad things for drivers that can't read status on all its pins. It is only affecting debugfs information quality. - Label descriptors with the device name if no explicit label is passed in. - Pave the ground for transitioning SPI and regulators to use GPIO descriptors by implementing some quirks in the device tree GPIO parsing code. New drivers: - New driver for the Access PCIe IDIO 24 family. Other: - Major refactorings and improvements to the GPIO mockup driver used for test and verification. - Moved the AXP209 driver over to pin control since it gained a pin control back-end. These patches will appear (with the same hashes) in the pin control pull request as well. - Convert the onewire GPIO driver w1-gpio to use descriptors. This is merged here since the W1 maintainers send very few pull requests and he ACKed it. - Start to clean up driver headers using <linux/gpio.h> to just use <linux/gpio/driver.h> as appropriate. -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJacIW6AAoJEEEQszewGV1z9b0P/jxWKaCAGFTTu/HZQ79RBAFq w33nIazzoh+88sN7A9xKexpr4ibOxiCvOwkTtrUBNaxGGy5fslj4+OY5BzunEfBK 1vYxyEqtenvvZK03pOd6CSfHKV+vD5ngnVHGdtGzRvtmDDiSgtzqyEyUhQcXM+l7 PrEh6qrd4TBZezlVR8kn5eqcmclkCBVSQCuLSq+ThMmCKRZuOdf1Im3D6eBzh1/N P81HdcglqbSsfUl1RcFiHs9Z+KcZOq83CNl2Ej1LePK2JBZbmkx9dR+WSJmV1u4P 6wvzFcQDhfGEiiteg2BS5c+o6aAyShpuRNut+2MLre8icmdfpqUEqFotHbfQjW5y sqaejGsJ5aHcRBq7UUM+F9s1R0iN3tlafi3L0WEhl0Tn5huRQq3Uqcw6e5l+XrWd 0h+b5PbKJZO/iqzRhSl+rhc0V2CFDJOCwvY+JX6356fvrcF0T6LhvKfDYtKU3Iyb HB0RG1OcYe228f96azvafCkFyBIYX9mqHBvOXpQQgrZQYXfN1rupLvpOhxC+Wbvn nsGE2bdD6HA1bytTbkxbL+QWP7faHf5YVcZpaN7UWbO3sOzL46fj8eHwHUim95Tr pR5kDZRhZd8+9SCNZ/ttpaEbis9MOqS/3Mlxrj4GXtfFFmR53hjFy2bG/Z7R2RB0 MlSEJRc8iDIs+1j3D2RR =k5nL -----END PGP SIGNATURE----- Merge tag 'gpio-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio Pull GPIO updates from Linus Walleij: "The is the bulk of GPIO changes for the v4.16 kernel cycle. It is pretty calm this time around I think. I even got time to get to things like starting to clean up header includes. Core changes: - Disallow open drain and open source flags to be set simultaneously. This doesn't make electrical sense, and would the hardware actually respond to this setting, the result would be short circuit. - ACPI GPIO has a new core infrastructure for handling quirks. The quirks are there to deal with broken ACPI tables centrally instead of pushing the work to individual drivers. In the world of BIOS writers, the ACPI tables are perfect. Until they find a mistake in it. When such a mistake is found, we can patch it with a quirk. It should never happen, the problem is that it happens. So we accomodate for it. - Several documentation updates. - Revert the patch setting up initial direction state from reading the device. This was causing bad things for drivers that can't read status on all its pins. It is only affecting debugfs information quality. - Label descriptors with the device name if no explicit label is passed in. - Pave the ground for transitioning SPI and regulators to use GPIO descriptors by implementing some quirks in the device tree GPIO parsing code. New drivers: - New driver for the Access PCIe IDIO 24 family. Other: - Major refactorings and improvements to the GPIO mockup driver used for test and verification. - Moved the AXP209 driver over to pin control since it gained a pin control back-end. These patches will appear (with the same hashes) in the pin control pull request as well. - Convert the onewire GPIO driver w1-gpio to use descriptors. This is merged here since the W1 maintainers send very few pull requests and he ACKed it. - Start to clean up driver headers using <linux/gpio.h> to just use <linux/gpio/driver.h> as appropriate" * tag 'gpio-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (103 commits) gpio: Timestamp events in hardirq handler gpio: Fix kernel stack leak to userspace gpio: Fix a documentation spelling mistake gpio: Documentation update gpiolib: remove redundant initialization of pointer desc gpio: of: Fix NPE from OF flags gpio: stmpe: Delete an unnecessary variable initialisation in stmpe_gpio_probe() gpio: stmpe: Move an assignment in stmpe_gpio_probe() gpio: stmpe: Improve a size determination in stmpe_gpio_probe() gpio: stmpe: Use seq_putc() in stmpe_dbg_show() gpio: No NULL owner gpio: stmpe: i2c transfer are forbiden in atomic context gpio: davinci: Include proper header gpio: da905x: Include proper header gpio: cs5535: Include proper header gpio: crystalcove: Include proper header gpio: bt8xx: Include proper header gpio: bcm-kona: Include proper header gpio: arizona: Include proper header gpio: amd8111: Include proper header ...
677 lines
18 KiB
C
677 lines
18 KiB
C
/*
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* Broadcom Kona GPIO Driver
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*
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* Author: Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>
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* Copyright (C) 2012-2014 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/gpio/driver.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/init.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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#define BCM_GPIO_PASSWD 0x00a5a501
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#define GPIO_PER_BANK 32
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#define GPIO_MAX_BANK_NUM 8
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#define GPIO_BANK(gpio) ((gpio) >> 5)
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#define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1))
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/* There is a GPIO control register for each GPIO */
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#define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2))
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/* The remaining registers are per GPIO bank */
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#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
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#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
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#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
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#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
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#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
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#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
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#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
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#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
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#define GPIO_GPPWR_OFFSET 0x00000520
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#define GPIO_GPCTR0_DBR_SHIFT 5
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#define GPIO_GPCTR0_DBR_MASK 0x000001e0
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#define GPIO_GPCTR0_ITR_SHIFT 3
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#define GPIO_GPCTR0_ITR_MASK 0x00000018
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#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001
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#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002
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#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003
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#define GPIO_GPCTR0_IOTR_MASK 0x00000001
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#define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000
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#define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001
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#define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100
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#define LOCK_CODE 0xffffffff
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#define UNLOCK_CODE 0x00000000
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struct bcm_kona_gpio {
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void __iomem *reg_base;
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int num_bank;
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raw_spinlock_t lock;
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struct gpio_chip gpio_chip;
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struct irq_domain *irq_domain;
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struct bcm_kona_gpio_bank *banks;
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struct platform_device *pdev;
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};
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struct bcm_kona_gpio_bank {
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int id;
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int irq;
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/* Used in the interrupt handler */
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struct bcm_kona_gpio *kona_gpio;
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};
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static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
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int bank_id, u32 lockcode)
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{
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writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
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writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
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}
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static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
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unsigned gpio)
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{
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u32 val;
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unsigned long flags;
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int bank_id = GPIO_BANK(gpio);
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
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val |= BIT(gpio);
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bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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}
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static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
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unsigned gpio)
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{
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u32 val;
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unsigned long flags;
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int bank_id = GPIO_BANK(gpio);
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
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val &= ~BIT(gpio);
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bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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}
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static int bcm_kona_gpio_get_dir(struct gpio_chip *chip, unsigned gpio)
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{
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struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
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void __iomem *reg_base = kona_gpio->reg_base;
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u32 val;
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val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;
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return !!val;
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}
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static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
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{
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struct bcm_kona_gpio *kona_gpio;
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void __iomem *reg_base;
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int bank_id = GPIO_BANK(gpio);
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int bit = GPIO_BIT(gpio);
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u32 val, reg_offset;
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unsigned long flags;
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kona_gpio = gpiochip_get_data(chip);
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reg_base = kona_gpio->reg_base;
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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/* this function only applies to output pin */
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if (bcm_kona_gpio_get_dir(chip, gpio) == 1)
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goto out;
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reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
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val = readl(reg_base + reg_offset);
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val |= BIT(bit);
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writel(val, reg_base + reg_offset);
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out:
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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}
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static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
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{
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struct bcm_kona_gpio *kona_gpio;
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void __iomem *reg_base;
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int bank_id = GPIO_BANK(gpio);
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int bit = GPIO_BIT(gpio);
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u32 val, reg_offset;
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unsigned long flags;
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kona_gpio = gpiochip_get_data(chip);
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reg_base = kona_gpio->reg_base;
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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if (bcm_kona_gpio_get_dir(chip, gpio) == 1)
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reg_offset = GPIO_IN_STATUS(bank_id);
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else
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reg_offset = GPIO_OUT_STATUS(bank_id);
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/* read the GPIO bank status */
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val = readl(reg_base + reg_offset);
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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/* return the specified bit status */
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return !!(val & BIT(bit));
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}
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static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio)
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{
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struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
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bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
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return 0;
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}
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static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio)
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{
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struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
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bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
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}
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static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
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{
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struct bcm_kona_gpio *kona_gpio;
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void __iomem *reg_base;
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u32 val;
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unsigned long flags;
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kona_gpio = gpiochip_get_data(chip);
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reg_base = kona_gpio->reg_base;
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(reg_base + GPIO_CONTROL(gpio));
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val &= ~GPIO_GPCTR0_IOTR_MASK;
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val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
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writel(val, reg_base + GPIO_CONTROL(gpio));
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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return 0;
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}
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static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
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unsigned gpio, int value)
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{
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struct bcm_kona_gpio *kona_gpio;
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void __iomem *reg_base;
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int bank_id = GPIO_BANK(gpio);
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int bit = GPIO_BIT(gpio);
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u32 val, reg_offset;
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unsigned long flags;
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kona_gpio = gpiochip_get_data(chip);
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reg_base = kona_gpio->reg_base;
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(reg_base + GPIO_CONTROL(gpio));
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val &= ~GPIO_GPCTR0_IOTR_MASK;
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val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
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writel(val, reg_base + GPIO_CONTROL(gpio));
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reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
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val = readl(reg_base + reg_offset);
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val |= BIT(bit);
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writel(val, reg_base + reg_offset);
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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return 0;
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}
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static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
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{
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struct bcm_kona_gpio *kona_gpio;
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kona_gpio = gpiochip_get_data(chip);
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if (gpio >= kona_gpio->gpio_chip.ngpio)
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return -ENXIO;
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return irq_create_mapping(kona_gpio->irq_domain, gpio);
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}
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static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
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unsigned debounce)
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{
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struct bcm_kona_gpio *kona_gpio;
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void __iomem *reg_base;
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u32 val, res;
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unsigned long flags;
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kona_gpio = gpiochip_get_data(chip);
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reg_base = kona_gpio->reg_base;
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/* debounce must be 1-128ms (or 0) */
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if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
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dev_err(chip->parent, "Debounce value %u not in range\n",
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debounce);
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return -EINVAL;
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}
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/* calculate debounce bit value */
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if (debounce != 0) {
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/* Convert to ms */
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debounce /= 1000;
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/* find the MSB */
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res = fls(debounce) - 1;
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/* Check if MSB-1 is set (round up or down) */
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if (res > 0 && (debounce & BIT(res - 1)))
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res++;
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}
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/* spin lock for read-modify-write of the GPIO register */
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(reg_base + GPIO_CONTROL(gpio));
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val &= ~GPIO_GPCTR0_DBR_MASK;
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if (debounce == 0) {
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/* disable debounce */
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val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
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} else {
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val |= GPIO_GPCTR0_DB_ENABLE_MASK |
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(res << GPIO_GPCTR0_DBR_SHIFT);
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}
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writel(val, reg_base + GPIO_CONTROL(gpio));
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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return 0;
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}
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static int bcm_kona_gpio_set_config(struct gpio_chip *chip, unsigned gpio,
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unsigned long config)
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{
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u32 debounce;
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if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
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return -ENOTSUPP;
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debounce = pinconf_to_config_argument(config);
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return bcm_kona_gpio_set_debounce(chip, gpio, debounce);
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}
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static const struct gpio_chip template_chip = {
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.label = "bcm-kona-gpio",
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.owner = THIS_MODULE,
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.request = bcm_kona_gpio_request,
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.free = bcm_kona_gpio_free,
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.get_direction = bcm_kona_gpio_get_dir,
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.direction_input = bcm_kona_gpio_direction_input,
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.get = bcm_kona_gpio_get,
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.direction_output = bcm_kona_gpio_direction_output,
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.set = bcm_kona_gpio_set,
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.set_config = bcm_kona_gpio_set_config,
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.to_irq = bcm_kona_gpio_to_irq,
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.base = 0,
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};
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static void bcm_kona_gpio_irq_ack(struct irq_data *d)
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{
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struct bcm_kona_gpio *kona_gpio;
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void __iomem *reg_base;
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unsigned gpio = d->hwirq;
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int bank_id = GPIO_BANK(gpio);
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int bit = GPIO_BIT(gpio);
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u32 val;
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unsigned long flags;
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kona_gpio = irq_data_get_irq_chip_data(d);
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reg_base = kona_gpio->reg_base;
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(reg_base + GPIO_INT_STATUS(bank_id));
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val |= BIT(bit);
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writel(val, reg_base + GPIO_INT_STATUS(bank_id));
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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}
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static void bcm_kona_gpio_irq_mask(struct irq_data *d)
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{
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struct bcm_kona_gpio *kona_gpio;
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void __iomem *reg_base;
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unsigned gpio = d->hwirq;
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int bank_id = GPIO_BANK(gpio);
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int bit = GPIO_BIT(gpio);
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u32 val;
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unsigned long flags;
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kona_gpio = irq_data_get_irq_chip_data(d);
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reg_base = kona_gpio->reg_base;
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(reg_base + GPIO_INT_MASK(bank_id));
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val |= BIT(bit);
|
|
writel(val, reg_base + GPIO_INT_MASK(bank_id));
|
|
|
|
raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
|
|
}
|
|
|
|
static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
|
|
{
|
|
struct bcm_kona_gpio *kona_gpio;
|
|
void __iomem *reg_base;
|
|
unsigned gpio = d->hwirq;
|
|
int bank_id = GPIO_BANK(gpio);
|
|
int bit = GPIO_BIT(gpio);
|
|
u32 val;
|
|
unsigned long flags;
|
|
|
|
kona_gpio = irq_data_get_irq_chip_data(d);
|
|
reg_base = kona_gpio->reg_base;
|
|
raw_spin_lock_irqsave(&kona_gpio->lock, flags);
|
|
|
|
val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
|
|
val |= BIT(bit);
|
|
writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
|
|
|
|
raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
|
|
}
|
|
|
|
static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
|
|
{
|
|
struct bcm_kona_gpio *kona_gpio;
|
|
void __iomem *reg_base;
|
|
unsigned gpio = d->hwirq;
|
|
u32 lvl_type;
|
|
u32 val;
|
|
unsigned long flags;
|
|
|
|
kona_gpio = irq_data_get_irq_chip_data(d);
|
|
reg_base = kona_gpio->reg_base;
|
|
switch (type & IRQ_TYPE_SENSE_MASK) {
|
|
case IRQ_TYPE_EDGE_RISING:
|
|
lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
|
|
break;
|
|
|
|
case IRQ_TYPE_EDGE_FALLING:
|
|
lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
|
|
break;
|
|
|
|
case IRQ_TYPE_EDGE_BOTH:
|
|
lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
|
|
break;
|
|
|
|
case IRQ_TYPE_LEVEL_HIGH:
|
|
case IRQ_TYPE_LEVEL_LOW:
|
|
/* BCM GPIO doesn't support level triggering */
|
|
default:
|
|
dev_err(kona_gpio->gpio_chip.parent,
|
|
"Invalid BCM GPIO irq type 0x%x\n", type);
|
|
return -EINVAL;
|
|
}
|
|
|
|
raw_spin_lock_irqsave(&kona_gpio->lock, flags);
|
|
|
|
val = readl(reg_base + GPIO_CONTROL(gpio));
|
|
val &= ~GPIO_GPCTR0_ITR_MASK;
|
|
val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
|
|
writel(val, reg_base + GPIO_CONTROL(gpio));
|
|
|
|
raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void bcm_kona_gpio_irq_handler(struct irq_desc *desc)
|
|
{
|
|
void __iomem *reg_base;
|
|
int bit, bank_id;
|
|
unsigned long sta;
|
|
struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc);
|
|
struct irq_chip *chip = irq_desc_get_chip(desc);
|
|
|
|
chained_irq_enter(chip, desc);
|
|
|
|
/*
|
|
* For bank interrupts, we can't use chip_data to store the kona_gpio
|
|
* pointer, since GIC needs it for its own purposes. Therefore, we get
|
|
* our pointer from the bank structure.
|
|
*/
|
|
reg_base = bank->kona_gpio->reg_base;
|
|
bank_id = bank->id;
|
|
|
|
while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
|
|
(~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
|
|
for_each_set_bit(bit, &sta, 32) {
|
|
int hwirq = GPIO_PER_BANK * bank_id + bit;
|
|
int child_irq =
|
|
irq_find_mapping(bank->kona_gpio->irq_domain,
|
|
hwirq);
|
|
/*
|
|
* Clear interrupt before handler is called so we don't
|
|
* miss any interrupt occurred during executing them.
|
|
*/
|
|
writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
|
|
BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
|
|
/* Invoke interrupt handler */
|
|
generic_handle_irq(child_irq);
|
|
}
|
|
}
|
|
|
|
chained_irq_exit(chip, desc);
|
|
}
|
|
|
|
static int bcm_kona_gpio_irq_reqres(struct irq_data *d)
|
|
{
|
|
struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
|
|
|
|
if (gpiochip_lock_as_irq(&kona_gpio->gpio_chip, d->hwirq)) {
|
|
dev_err(kona_gpio->gpio_chip.parent,
|
|
"unable to lock HW IRQ %lu for IRQ\n",
|
|
d->hwirq);
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void bcm_kona_gpio_irq_relres(struct irq_data *d)
|
|
{
|
|
struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
|
|
|
|
gpiochip_unlock_as_irq(&kona_gpio->gpio_chip, d->hwirq);
|
|
}
|
|
|
|
static struct irq_chip bcm_gpio_irq_chip = {
|
|
.name = "bcm-kona-gpio",
|
|
.irq_ack = bcm_kona_gpio_irq_ack,
|
|
.irq_mask = bcm_kona_gpio_irq_mask,
|
|
.irq_unmask = bcm_kona_gpio_irq_unmask,
|
|
.irq_set_type = bcm_kona_gpio_irq_set_type,
|
|
.irq_request_resources = bcm_kona_gpio_irq_reqres,
|
|
.irq_release_resources = bcm_kona_gpio_irq_relres,
|
|
};
|
|
|
|
static struct of_device_id const bcm_kona_gpio_of_match[] = {
|
|
{ .compatible = "brcm,kona-gpio" },
|
|
{}
|
|
};
|
|
|
|
/*
|
|
* This lock class tells lockdep that GPIO irqs are in a different
|
|
* category than their parents, so it won't report false recursion.
|
|
*/
|
|
static struct lock_class_key gpio_lock_class;
|
|
static struct lock_class_key gpio_request_class;
|
|
|
|
static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
|
|
irq_hw_number_t hwirq)
|
|
{
|
|
int ret;
|
|
|
|
ret = irq_set_chip_data(irq, d->host_data);
|
|
if (ret < 0)
|
|
return ret;
|
|
irq_set_lockdep_class(irq, &gpio_lock_class, &gpio_request_class);
|
|
irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
|
|
irq_set_noprobe(irq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
|
|
{
|
|
irq_set_chip_and_handler(irq, NULL, NULL);
|
|
irq_set_chip_data(irq, NULL);
|
|
}
|
|
|
|
static const struct irq_domain_ops bcm_kona_irq_ops = {
|
|
.map = bcm_kona_gpio_irq_map,
|
|
.unmap = bcm_kona_gpio_irq_unmap,
|
|
.xlate = irq_domain_xlate_twocell,
|
|
};
|
|
|
|
static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
|
|
{
|
|
void __iomem *reg_base;
|
|
int i;
|
|
|
|
reg_base = kona_gpio->reg_base;
|
|
/* disable interrupts and clear status */
|
|
for (i = 0; i < kona_gpio->num_bank; i++) {
|
|
/* Unlock the entire bank first */
|
|
bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE);
|
|
writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
|
|
writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
|
|
/* Now re-lock the bank */
|
|
bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE);
|
|
}
|
|
}
|
|
|
|
static int bcm_kona_gpio_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
const struct of_device_id *match;
|
|
struct resource *res;
|
|
struct bcm_kona_gpio_bank *bank;
|
|
struct bcm_kona_gpio *kona_gpio;
|
|
struct gpio_chip *chip;
|
|
int ret;
|
|
int i;
|
|
|
|
match = of_match_device(bcm_kona_gpio_of_match, dev);
|
|
if (!match) {
|
|
dev_err(dev, "Failed to find gpio controller\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
|
|
if (!kona_gpio)
|
|
return -ENOMEM;
|
|
|
|
kona_gpio->gpio_chip = template_chip;
|
|
chip = &kona_gpio->gpio_chip;
|
|
kona_gpio->num_bank = of_irq_count(dev->of_node);
|
|
if (kona_gpio->num_bank == 0) {
|
|
dev_err(dev, "Couldn't determine # GPIO banks\n");
|
|
return -ENOENT;
|
|
}
|
|
if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
|
|
dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
|
|
GPIO_MAX_BANK_NUM);
|
|
return -ENXIO;
|
|
}
|
|
kona_gpio->banks = devm_kzalloc(dev,
|
|
kona_gpio->num_bank *
|
|
sizeof(*kona_gpio->banks), GFP_KERNEL);
|
|
if (!kona_gpio->banks)
|
|
return -ENOMEM;
|
|
|
|
kona_gpio->pdev = pdev;
|
|
platform_set_drvdata(pdev, kona_gpio);
|
|
chip->of_node = dev->of_node;
|
|
chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
|
|
|
|
kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node,
|
|
chip->ngpio,
|
|
&bcm_kona_irq_ops,
|
|
kona_gpio);
|
|
if (!kona_gpio->irq_domain) {
|
|
dev_err(dev, "Couldn't allocate IRQ domain\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
kona_gpio->reg_base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(kona_gpio->reg_base)) {
|
|
ret = -ENXIO;
|
|
goto err_irq_domain;
|
|
}
|
|
|
|
for (i = 0; i < kona_gpio->num_bank; i++) {
|
|
bank = &kona_gpio->banks[i];
|
|
bank->id = i;
|
|
bank->irq = platform_get_irq(pdev, i);
|
|
bank->kona_gpio = kona_gpio;
|
|
if (bank->irq < 0) {
|
|
dev_err(dev, "Couldn't get IRQ for bank %d", i);
|
|
ret = -ENOENT;
|
|
goto err_irq_domain;
|
|
}
|
|
}
|
|
|
|
dev_info(&pdev->dev, "Setting up Kona GPIO\n");
|
|
|
|
bcm_kona_gpio_reset(kona_gpio);
|
|
|
|
ret = devm_gpiochip_add_data(dev, chip, kona_gpio);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
|
|
goto err_irq_domain;
|
|
}
|
|
for (i = 0; i < kona_gpio->num_bank; i++) {
|
|
bank = &kona_gpio->banks[i];
|
|
irq_set_chained_handler_and_data(bank->irq,
|
|
bcm_kona_gpio_irq_handler,
|
|
bank);
|
|
}
|
|
|
|
raw_spin_lock_init(&kona_gpio->lock);
|
|
|
|
return 0;
|
|
|
|
err_irq_domain:
|
|
irq_domain_remove(kona_gpio->irq_domain);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct platform_driver bcm_kona_gpio_driver = {
|
|
.driver = {
|
|
.name = "bcm-kona-gpio",
|
|
.of_match_table = bcm_kona_gpio_of_match,
|
|
},
|
|
.probe = bcm_kona_gpio_probe,
|
|
};
|
|
builtin_platform_driver(bcm_kona_gpio_driver);
|