mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-11 22:26:41 +07:00
1a8a51004a
Impact: cleanup It's unused, since about 1995. So remove all initialization of it in preparation for actually removing the field. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Acked-by: Thomas Gleixner <tglx@linutronix.de>
103 lines
1.9 KiB
C
103 lines
1.9 KiB
C
/*
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* linux/arch/h8300/kernel/cpu/timer/timer8.c
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*
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* Yoshinori Sato <ysato@users.sourcefoge.jp>
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*
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* 8bit Timer Handler
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*
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*/
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/profile.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/timer.h>
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#if defined(CONFIG_CPU_H8300H)
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#include <asm/regs306x.h>
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#endif
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#if defined(CONFIG_CPU_H8S)
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#include <asm/regs267x.h>
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#endif
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/* 8bit timer x2 */
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#define CMFA 6
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#if defined(CONFIG_H8300_TIMER8_CH0)
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#define _8BASE _8TCR0
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#ifdef CONFIG_CPU_H8300H
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#define _8IRQ 36
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#endif
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#ifdef CONFIG_CPU_H8S
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#define _8IRQ 72
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#endif
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#elif defined(CONFIG_H8300_TIMER8_CH2)
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#ifdef CONFIG_CPU_H8300H
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#define _8BASE _8TCR2
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#define _8IRQ 40
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#endif
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#endif
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#ifndef _8BASE
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#error Unknown timer channel.
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#endif
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#define _8TCR 0
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#define _8TCSR 2
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#define TCORA 4
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#define TCORB 6
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#define _8TCNT 8
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#define CMIEA 0x40
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#define CCLR_CMA 0x08
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#define CKS2 0x04
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/*
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* timer_interrupt() needs to keep up the real-time clock,
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* as well as call the "do_timer()" routine every clocktick
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*/
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static irqreturn_t timer_interrupt(int irq, void *dev_id)
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{
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h8300_timer_tick();
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ctrl_bclr(CMFA, _8BASE + _8TCSR);
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return IRQ_HANDLED;
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}
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static struct irqaction timer8_irq = {
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.name = "timer-8",
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.handler = timer_interrupt,
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.flags = IRQF_DISABLED | IRQF_TIMER,
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};
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static const int __initdata divide_rate[] = {8, 64, 8192};
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void __init h8300_timer_setup(void)
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{
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unsigned int div;
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unsigned int cnt;
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calc_param(cnt, div, divide_rate, 0x10000);
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div++;
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setup_irq(_8IRQ, &timer8_irq);
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#if defined(CONFIG_CPU_H8S)
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/* Timer module enable */
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ctrl_bclr(0, MSTPCRL)
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#endif
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/* initalize timer */
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ctrl_outw(cnt, _8BASE + TCORA);
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ctrl_outw(0x0000, _8BASE + _8TCSR);
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ctrl_outw((CMIEA|CCLR_CMA|CKS2) << 8 | div,
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_8BASE + _8TCR);
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}
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