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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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7a5d73479f
LS1088A contains eight ARM v8 CortexA53 processor cores
with 32 KB L1-D cache and 32 KB L1-I cache
Features summary
Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs
- Arranged as two clusters of four cores sharing a 1 MB L2 cache
- Speed Up to 1.5 GHz
- Support for cluster power-gating.
Cache coherent interconnect (CCI-400)
- Hardware-managed data coherency
- Up to 700 MHz
One 64-bit DDR4 SDRAM memory controller with ECC
Data path acceleration architecture 2.0 (DPAA2)
Three PCIe 3.0 controllers
One serial ATA (SATA 3.0) controller
Three high-speed USB 3.0 controllers with integrated PHY
Following levels of DTSI/DTS files have been created for the LS1088A
SoC family:
- fsl-ls1088a.dtsi:
DTS-Include file for NXP LS1088A SoC.
- fsl-ls1088a-qds.dts:
DTS file for NXP LS1088A QDS board.
- fsl-ls1088a-rdb.dts:
DTS file for NXP LS1088A RDB board
Signed-off-by: Harninder Rai <harninder.rai@nxp.com>
Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>`
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
276 lines
7.2 KiB
Plaintext
276 lines
7.2 KiB
Plaintext
/*
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* Device Tree Include file for NXP Layerscape-1088A family SoC.
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*
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* Copyright 2017 NXP
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*
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* Harninder Rai <harninder.rai@nxp.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPLv2 or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "fsl,ls1088a";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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/* We have 2 clusters having 4 Cortex-A53 cores each */
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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clocks = <&clockgen 1 0>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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clocks = <&clockgen 1 0>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x2>;
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clocks = <&clockgen 1 0>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x3>;
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clocks = <&clockgen 1 0>;
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};
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cpu4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x100>;
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clocks = <&clockgen 1 1>;
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};
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cpu5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x101>;
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clocks = <&clockgen 1 1>;
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};
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cpu6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x102>;
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clocks = <&clockgen 1 1>;
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};
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cpu7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x103>;
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clocks = <&clockgen 1 1>;
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};
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};
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gic: interrupt-controller@6000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
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<0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
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<0x0 0x0c0c0000 0 0x2000>, /* GICC */
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<0x0 0x0c0d0000 0 0x1000>, /* GICH */
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<0x0 0x0c0e0000 0 0x20000>; /* GICV */
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interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
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<1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
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<1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
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<1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
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};
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sysclk: sysclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "sysclk";
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clockgen: clocking@1300000 {
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compatible = "fsl,ls1088a-clockgen";
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reg = <0 0x1300000 0 0xa0000>;
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#clock-cells = <2>;
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clocks = <&sysclk>;
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};
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duart0: serial@21c0500 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21c0500 0x0 0x100>;
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clocks = <&clockgen 4 3>;
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interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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duart1: serial@21c0600 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21c0600 0x0 0x100>;
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clocks = <&clockgen 4 3>;
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interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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gpio0: gpio@2300000 {
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compatible = "fsl,qoriq-gpio";
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reg = <0x0 0x2300000 0x0 0x10000>;
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interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio@2310000 {
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compatible = "fsl,qoriq-gpio";
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reg = <0x0 0x2310000 0x0 0x10000>;
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interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@2320000 {
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compatible = "fsl,qoriq-gpio";
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reg = <0x0 0x2320000 0x0 0x10000>;
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interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@2330000 {
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compatible = "fsl,qoriq-gpio";
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reg = <0x0 0x2330000 0x0 0x10000>;
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interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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ifc: ifc@2240000 {
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compatible = "fsl,ifc", "simple-bus";
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reg = <0x0 0x2240000 0x0 0x20000>;
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interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
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little-endian;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x5 0x80000000 0x08000000
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2 0 0x5 0x30000000 0x00010000
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3 0 0x5 0x20000000 0x00010000>;
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status = "disabled";
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};
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i2c0: i2c@2000000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2000000 0x0 0x10000>;
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interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 3>;
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status = "disabled";
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};
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i2c1: i2c@2010000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2010000 0x0 0x10000>;
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interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 3>;
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status = "disabled";
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};
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i2c2: i2c@2020000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2020000 0x0 0x10000>;
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interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 3>;
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status = "disabled";
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};
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i2c3: i2c@2030000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2030000 0x0 0x10000>;
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interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 3>;
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status = "disabled";
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};
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sata: sata@3200000 {
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compatible = "fsl,ls1088a-ahci", "fsl,ls1043a-ahci";
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reg = <0x0 0x3200000 0x0 0x10000>;
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interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 3>;
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status = "disabled";
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};
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};
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};
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