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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 06:46:59 +07:00
d86b8da04d
Boqun Feng reported a rather nasty ordering issue with spin_unlock_wait on architectures implementing spin_lock with LL/SC sequences and acquire semantics: | CPU 1 CPU 2 CPU 3 | ================== ==================== ============== | spin_unlock(&lock); | spin_lock(&lock): | r1 = *lock; // r1 == 0; | o = READ_ONCE(object); // reordered here | object = NULL; | smp_mb(); | spin_unlock_wait(&lock); | *lock = 1; | smp_mb(); | o->dead = true; | if (o) // true | BUG_ON(o->dead); // true!! The crux of the problem is that spin_unlock_wait(&lock) can return on CPU 1 whilst CPU 2 is in the process of taking the lock. This can be resolved by upgrading spin_unlock_wait to a LOCK operation, forcing it to serialise against a concurrent locker and giving it acquire semantics in the process (although it is not at all clear whether this is needed - different callers seem to assume different things about the barrier semantics and architectures are similarly disjoint in their implementations of the macro). This patch implements spin_unlock_wait using an LL/SC sequence with acquire semantics on arm64. For v8.1 systems with the LSE atomics, the exclusive writeback is omitted, since the spin_lock operation is indivisible and no intermediate state can be observed. Signed-off-by: Will Deacon <will.deacon@arm.com>
335 lines
7.2 KiB
C
335 lines
7.2 KiB
C
/*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_SPINLOCK_H
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#define __ASM_SPINLOCK_H
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#include <asm/lse.h>
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#include <asm/spinlock_types.h>
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#include <asm/processor.h>
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/*
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* Spinlock implementation.
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*
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* The memory barriers are implicit with the load-acquire and store-release
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* instructions.
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*/
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static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
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{
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unsigned int tmp;
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arch_spinlock_t lockval;
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asm volatile(
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" sevl\n"
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"1: wfe\n"
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"2: ldaxr %w0, %2\n"
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" eor %w1, %w0, %w0, ror #16\n"
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" cbnz %w1, 1b\n"
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ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" stxr %w1, %w0, %2\n"
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" cbnz %w1, 2b\n", /* Serialise against any concurrent lockers */
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/* LSE atomics */
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" nop\n"
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" nop\n")
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: "=&r" (lockval), "=&r" (tmp), "+Q" (*lock)
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:
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: "memory");
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}
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#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
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static inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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unsigned int tmp;
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arch_spinlock_t lockval, newval;
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asm volatile(
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/* Atomically increment the next ticket. */
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ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" prfm pstl1strm, %3\n"
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"1: ldaxr %w0, %3\n"
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" add %w1, %w0, %w5\n"
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" stxr %w2, %w1, %3\n"
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" cbnz %w2, 1b\n",
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/* LSE atomics */
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" mov %w2, %w5\n"
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" ldadda %w2, %w0, %3\n"
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" nop\n"
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" nop\n"
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" nop\n"
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)
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/* Did we get the lock? */
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" eor %w1, %w0, %w0, ror #16\n"
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" cbz %w1, 3f\n"
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/*
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* No: spin on the owner. Send a local event to avoid missing an
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* unlock before the exclusive load.
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*/
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" sevl\n"
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"2: wfe\n"
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" ldaxrh %w2, %4\n"
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" eor %w1, %w2, %w0, lsr #16\n"
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" cbnz %w1, 2b\n"
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/* We got the lock. Critical section starts here. */
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"3:"
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: "=&r" (lockval), "=&r" (newval), "=&r" (tmp), "+Q" (*lock)
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: "Q" (lock->owner), "I" (1 << TICKET_SHIFT)
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: "memory");
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}
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static inline int arch_spin_trylock(arch_spinlock_t *lock)
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{
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unsigned int tmp;
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arch_spinlock_t lockval;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" prfm pstl1strm, %2\n"
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"1: ldaxr %w0, %2\n"
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" eor %w1, %w0, %w0, ror #16\n"
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" cbnz %w1, 2f\n"
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" add %w0, %w0, %3\n"
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" stxr %w1, %w0, %2\n"
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" cbnz %w1, 1b\n"
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"2:",
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/* LSE atomics */
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" ldr %w0, %2\n"
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" eor %w1, %w0, %w0, ror #16\n"
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" cbnz %w1, 1f\n"
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" add %w1, %w0, %3\n"
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" casa %w0, %w1, %2\n"
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" and %w1, %w1, #0xffff\n"
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" eor %w1, %w1, %w0, lsr #16\n"
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"1:")
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: "=&r" (lockval), "=&r" (tmp), "+Q" (*lock)
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: "I" (1 << TICKET_SHIFT)
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: "memory");
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return !tmp;
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}
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static inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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unsigned long tmp;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" ldrh %w1, %0\n"
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" add %w1, %w1, #1\n"
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" stlrh %w1, %0",
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/* LSE atomics */
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" mov %w1, #1\n"
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" nop\n"
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" staddlh %w1, %0")
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: "=Q" (lock->owner), "=&r" (tmp)
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:
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: "memory");
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}
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static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
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{
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return lock.owner == lock.next;
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}
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static inline int arch_spin_is_locked(arch_spinlock_t *lock)
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{
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return !arch_spin_value_unlocked(READ_ONCE(*lock));
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}
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static inline int arch_spin_is_contended(arch_spinlock_t *lock)
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{
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arch_spinlock_t lockval = READ_ONCE(*lock);
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return (lockval.next - lockval.owner) > 1;
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}
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#define arch_spin_is_contended arch_spin_is_contended
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/*
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* Write lock implementation.
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*
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* Write locks set bit 31. Unlocking, is done by writing 0 since the lock is
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* exclusively held.
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*
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* The memory barriers are implicit with the load-acquire and store-release
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* instructions.
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*/
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static inline void arch_write_lock(arch_rwlock_t *rw)
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{
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unsigned int tmp;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" sevl\n"
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"1: wfe\n"
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"2: ldaxr %w0, %1\n"
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" cbnz %w0, 1b\n"
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" stxr %w0, %w2, %1\n"
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" cbnz %w0, 2b\n"
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" nop",
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/* LSE atomics */
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"1: mov %w0, wzr\n"
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"2: casa %w0, %w2, %1\n"
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" cbz %w0, 3f\n"
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" ldxr %w0, %1\n"
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" cbz %w0, 2b\n"
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" wfe\n"
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" b 1b\n"
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"3:")
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: "=&r" (tmp), "+Q" (rw->lock)
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: "r" (0x80000000)
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: "memory");
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}
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static inline int arch_write_trylock(arch_rwlock_t *rw)
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{
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unsigned int tmp;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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"1: ldaxr %w0, %1\n"
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" cbnz %w0, 2f\n"
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" stxr %w0, %w2, %1\n"
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" cbnz %w0, 1b\n"
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"2:",
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/* LSE atomics */
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" mov %w0, wzr\n"
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" casa %w0, %w2, %1\n"
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" nop\n"
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" nop")
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: "=&r" (tmp), "+Q" (rw->lock)
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: "r" (0x80000000)
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: "memory");
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return !tmp;
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}
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static inline void arch_write_unlock(arch_rwlock_t *rw)
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{
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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" stlr wzr, %0",
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" swpl wzr, wzr, %0")
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: "=Q" (rw->lock) :: "memory");
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}
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/* write_can_lock - would write_trylock() succeed? */
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#define arch_write_can_lock(x) ((x)->lock == 0)
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/*
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* Read lock implementation.
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*
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* It exclusively loads the lock value, increments it and stores the new value
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* back if positive and the CPU still exclusively owns the location. If the
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* value is negative, the lock is already held.
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*
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* During unlocking there may be multiple active read locks but no write lock.
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*
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* The memory barriers are implicit with the load-acquire and store-release
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* instructions.
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*
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* Note that in UNDEFINED cases, such as unlocking a lock twice, the LL/SC
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* and LSE implementations may exhibit different behaviour (although this
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* will have no effect on lockdep).
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*/
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static inline void arch_read_lock(arch_rwlock_t *rw)
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{
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unsigned int tmp, tmp2;
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asm volatile(
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" sevl\n"
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ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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"1: wfe\n"
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"2: ldaxr %w0, %2\n"
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" add %w0, %w0, #1\n"
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" tbnz %w0, #31, 1b\n"
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" stxr %w1, %w0, %2\n"
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" nop\n"
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" cbnz %w1, 2b",
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/* LSE atomics */
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"1: wfe\n"
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"2: ldxr %w0, %2\n"
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" adds %w1, %w0, #1\n"
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" tbnz %w1, #31, 1b\n"
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" casa %w0, %w1, %2\n"
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" sbc %w0, %w1, %w0\n"
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" cbnz %w0, 2b")
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: "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
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:
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: "cc", "memory");
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}
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static inline void arch_read_unlock(arch_rwlock_t *rw)
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{
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unsigned int tmp, tmp2;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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"1: ldxr %w0, %2\n"
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" sub %w0, %w0, #1\n"
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" stlxr %w1, %w0, %2\n"
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" cbnz %w1, 1b",
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/* LSE atomics */
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" movn %w0, #0\n"
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" nop\n"
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" nop\n"
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" staddl %w0, %2")
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: "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
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:
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: "memory");
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}
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static inline int arch_read_trylock(arch_rwlock_t *rw)
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{
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unsigned int tmp, tmp2;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" mov %w1, #1\n"
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"1: ldaxr %w0, %2\n"
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" add %w0, %w0, #1\n"
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" tbnz %w0, #31, 2f\n"
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" stxr %w1, %w0, %2\n"
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" cbnz %w1, 1b\n"
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"2:",
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/* LSE atomics */
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" ldr %w0, %2\n"
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" adds %w1, %w0, #1\n"
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" tbnz %w1, #31, 1f\n"
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" casa %w0, %w1, %2\n"
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" sbc %w1, %w1, %w0\n"
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" nop\n"
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"1:")
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: "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
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:
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: "cc", "memory");
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return !tmp2;
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}
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/* read_can_lock - would read_trylock() succeed? */
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#define arch_read_can_lock(x) ((x)->lock < 0x80000000)
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#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
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#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
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#define arch_spin_relax(lock) cpu_relax()
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#define arch_read_relax(lock) cpu_relax()
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#define arch_write_relax(lock) cpu_relax()
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#endif /* __ASM_SPINLOCK_H */
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