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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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dbad75dd1f
KERNCZ GPIO is a new IP from AMD. it can be implemented in both x86 and ARM. Current driver patch only support GPIO in x86. Signed-off-by: Ken Xue <Ken.Xue@amd.com> [Moved back to <linux/gpio.h> header] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
262 lines
6.4 KiB
C
262 lines
6.4 KiB
C
/*
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* GPIO driver for AMD
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*
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* Copyright (c) 2014,2015 Ken Xue <Ken.Xue@amd.com>
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* Jeff Wu <Jeff.Wu@amd.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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*/
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#ifndef _PINCTRL_AMD_H
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#define _PINCTRL_AMD_H
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#define TOTAL_NUMBER_OF_PINS 192
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#define AMD_GPIO_PINS_PER_BANK 64
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#define AMD_GPIO_TOTAL_BANKS 3
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#define AMD_GPIO_PINS_BANK0 63
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#define AMD_GPIO_PINS_BANK1 64
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#define AMD_GPIO_PINS_BANK2 56
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#define WAKE_INT_MASTER_REG 0xfc
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#define EOI_MASK (1 << 29)
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#define WAKE_INT_STATUS_REG0 0x2f8
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#define WAKE_INT_STATUS_REG1 0x2fc
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#define DB_TMR_OUT_OFF 0
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#define DB_TMR_OUT_UNIT_OFF 4
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#define DB_CNTRL_OFF 5
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#define DB_TMR_LARGE_OFF 7
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#define LEVEL_TRIG_OFF 8
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#define ACTIVE_LEVEL_OFF 9
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#define INTERRUPT_ENABLE_OFF 11
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#define INTERRUPT_MASK_OFF 12
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#define WAKE_CNTRL_OFF 13
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#define PIN_STS_OFF 16
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#define DRV_STRENGTH_SEL_OFF 17
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#define PULL_UP_SEL_OFF 19
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#define PULL_UP_ENABLE_OFF 20
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#define PULL_DOWN_ENABLE_OFF 21
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#define OUTPUT_VALUE_OFF 22
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#define OUTPUT_ENABLE_OFF 23
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#define SW_CNTRL_IN_OFF 24
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#define SW_CNTRL_EN_OFF 25
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#define INTERRUPT_STS_OFF 28
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#define WAKE_STS_OFF 29
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#define DB_TMR_OUT_MASK 0xFUL
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#define DB_CNTRl_MASK 0x3UL
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#define ACTIVE_LEVEL_MASK 0x3UL
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#define DRV_STRENGTH_SEL_MASK 0x3UL
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#define DB_TYPE_NO_DEBOUNCE 0x0UL
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#define DB_TYPE_PRESERVE_LOW_GLITCH 0x1UL
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#define DB_TYPE_PRESERVE_HIGH_GLITCH 0x2UL
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#define DB_TYPE_REMOVE_GLITCH 0x3UL
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#define EDGE_TRAGGER 0x0UL
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#define LEVEL_TRIGGER 0x1UL
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#define ACTIVE_HIGH 0x0UL
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#define ACTIVE_LOW 0x1UL
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#define BOTH_EADGE 0x2UL
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#define ENABLE_INTERRUPT 0x1UL
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#define DISABLE_INTERRUPT 0x0UL
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#define ENABLE_INTERRUPT_MASK 0x0UL
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#define DISABLE_INTERRUPT_MASK 0x1UL
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#define CLR_INTR_STAT 0x1UL
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struct amd_pingroup {
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const char *name;
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const unsigned *pins;
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unsigned npins;
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};
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struct amd_function {
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const char *name;
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const char * const *groups;
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unsigned ngroups;
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};
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struct amd_gpio {
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spinlock_t lock;
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void __iomem *base;
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const struct amd_pingroup *groups;
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u32 ngroups;
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struct pinctrl_dev *pctrl;
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struct gpio_chip gc;
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struct resource *res;
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struct platform_device *pdev;
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};
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/* KERNCZ configuration*/
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static const struct pinctrl_pin_desc kerncz_pins[] = {
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PINCTRL_PIN(0, "GPIO_0"),
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PINCTRL_PIN(1, "GPIO_1"),
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PINCTRL_PIN(2, "GPIO_2"),
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PINCTRL_PIN(3, "GPIO_3"),
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PINCTRL_PIN(4, "GPIO_4"),
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PINCTRL_PIN(5, "GPIO_5"),
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PINCTRL_PIN(6, "GPIO_6"),
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PINCTRL_PIN(7, "GPIO_7"),
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PINCTRL_PIN(8, "GPIO_8"),
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PINCTRL_PIN(9, "GPIO_9"),
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PINCTRL_PIN(10, "GPIO_10"),
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PINCTRL_PIN(11, "GPIO_11"),
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PINCTRL_PIN(12, "GPIO_12"),
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PINCTRL_PIN(13, "GPIO_13"),
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PINCTRL_PIN(14, "GPIO_14"),
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PINCTRL_PIN(15, "GPIO_15"),
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PINCTRL_PIN(16, "GPIO_16"),
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PINCTRL_PIN(17, "GPIO_17"),
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PINCTRL_PIN(18, "GPIO_18"),
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PINCTRL_PIN(19, "GPIO_19"),
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PINCTRL_PIN(20, "GPIO_20"),
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PINCTRL_PIN(23, "GPIO_23"),
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PINCTRL_PIN(24, "GPIO_24"),
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PINCTRL_PIN(25, "GPIO_25"),
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PINCTRL_PIN(26, "GPIO_26"),
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PINCTRL_PIN(39, "GPIO_39"),
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PINCTRL_PIN(40, "GPIO_40"),
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PINCTRL_PIN(43, "GPIO_42"),
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PINCTRL_PIN(46, "GPIO_46"),
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PINCTRL_PIN(47, "GPIO_47"),
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PINCTRL_PIN(48, "GPIO_48"),
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PINCTRL_PIN(49, "GPIO_49"),
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PINCTRL_PIN(50, "GPIO_50"),
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PINCTRL_PIN(51, "GPIO_51"),
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PINCTRL_PIN(52, "GPIO_52"),
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PINCTRL_PIN(53, "GPIO_53"),
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PINCTRL_PIN(54, "GPIO_54"),
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PINCTRL_PIN(55, "GPIO_55"),
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PINCTRL_PIN(56, "GPIO_56"),
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PINCTRL_PIN(57, "GPIO_57"),
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PINCTRL_PIN(58, "GPIO_58"),
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PINCTRL_PIN(59, "GPIO_59"),
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PINCTRL_PIN(60, "GPIO_60"),
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PINCTRL_PIN(61, "GPIO_61"),
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PINCTRL_PIN(62, "GPIO_62"),
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PINCTRL_PIN(64, "GPIO_64"),
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PINCTRL_PIN(65, "GPIO_65"),
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PINCTRL_PIN(66, "GPIO_66"),
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PINCTRL_PIN(68, "GPIO_68"),
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PINCTRL_PIN(69, "GPIO_69"),
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PINCTRL_PIN(70, "GPIO_70"),
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PINCTRL_PIN(71, "GPIO_71"),
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PINCTRL_PIN(72, "GPIO_72"),
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PINCTRL_PIN(74, "GPIO_74"),
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PINCTRL_PIN(75, "GPIO_75"),
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PINCTRL_PIN(76, "GPIO_76"),
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PINCTRL_PIN(84, "GPIO_84"),
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PINCTRL_PIN(85, "GPIO_85"),
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PINCTRL_PIN(86, "GPIO_86"),
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PINCTRL_PIN(87, "GPIO_87"),
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PINCTRL_PIN(88, "GPIO_88"),
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PINCTRL_PIN(89, "GPIO_89"),
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PINCTRL_PIN(90, "GPIO_90"),
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PINCTRL_PIN(91, "GPIO_91"),
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PINCTRL_PIN(92, "GPIO_92"),
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PINCTRL_PIN(93, "GPIO_93"),
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PINCTRL_PIN(95, "GPIO_95"),
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PINCTRL_PIN(96, "GPIO_96"),
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PINCTRL_PIN(97, "GPIO_97"),
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PINCTRL_PIN(98, "GPIO_98"),
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PINCTRL_PIN(99, "GPIO_99"),
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PINCTRL_PIN(100, "GPIO_100"),
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PINCTRL_PIN(101, "GPIO_101"),
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PINCTRL_PIN(102, "GPIO_102"),
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PINCTRL_PIN(113, "GPIO_113"),
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PINCTRL_PIN(114, "GPIO_114"),
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PINCTRL_PIN(115, "GPIO_115"),
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PINCTRL_PIN(116, "GPIO_116"),
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PINCTRL_PIN(117, "GPIO_117"),
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PINCTRL_PIN(118, "GPIO_118"),
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PINCTRL_PIN(119, "GPIO_119"),
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PINCTRL_PIN(120, "GPIO_120"),
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PINCTRL_PIN(121, "GPIO_121"),
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PINCTRL_PIN(122, "GPIO_122"),
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PINCTRL_PIN(126, "GPIO_126"),
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PINCTRL_PIN(129, "GPIO_129"),
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PINCTRL_PIN(130, "GPIO_130"),
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PINCTRL_PIN(131, "GPIO_131"),
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PINCTRL_PIN(132, "GPIO_132"),
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PINCTRL_PIN(133, "GPIO_133"),
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PINCTRL_PIN(135, "GPIO_135"),
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PINCTRL_PIN(136, "GPIO_136"),
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PINCTRL_PIN(137, "GPIO_137"),
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PINCTRL_PIN(138, "GPIO_138"),
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PINCTRL_PIN(139, "GPIO_139"),
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PINCTRL_PIN(140, "GPIO_140"),
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PINCTRL_PIN(141, "GPIO_141"),
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PINCTRL_PIN(142, "GPIO_142"),
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PINCTRL_PIN(143, "GPIO_143"),
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PINCTRL_PIN(144, "GPIO_144"),
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PINCTRL_PIN(145, "GPIO_145"),
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PINCTRL_PIN(146, "GPIO_146"),
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PINCTRL_PIN(147, "GPIO_147"),
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PINCTRL_PIN(148, "GPIO_148"),
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PINCTRL_PIN(166, "GPIO_166"),
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PINCTRL_PIN(167, "GPIO_167"),
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PINCTRL_PIN(168, "GPIO_168"),
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PINCTRL_PIN(169, "GPIO_169"),
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PINCTRL_PIN(170, "GPIO_170"),
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PINCTRL_PIN(171, "GPIO_171"),
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PINCTRL_PIN(172, "GPIO_172"),
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PINCTRL_PIN(173, "GPIO_173"),
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PINCTRL_PIN(174, "GPIO_174"),
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PINCTRL_PIN(175, "GPIO_175"),
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PINCTRL_PIN(176, "GPIO_176"),
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PINCTRL_PIN(177, "GPIO_177"),
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};
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const unsigned i2c0_pins[] = {145, 146};
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const unsigned i2c1_pins[] = {147, 148};
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const unsigned i2c2_pins[] = {113, 114};
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const unsigned i2c3_pins[] = {19, 20};
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const unsigned uart0_pins[] = {135, 136, 137, 138, 139};
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const unsigned uart1_pins[] = {140, 141, 142, 143, 144};
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static const struct amd_pingroup kerncz_groups[] = {
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{
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.name = "i2c0",
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.pins = i2c0_pins,
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.npins = 2,
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},
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{
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.name = "i2c1",
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.pins = i2c1_pins,
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.npins = 2,
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},
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{
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.name = "i2c2",
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.pins = i2c2_pins,
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.npins = 2,
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},
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{
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.name = "i2c3",
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.pins = i2c3_pins,
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.npins = 2,
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},
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{
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.name = "uart0",
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.pins = uart0_pins,
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.npins = 9,
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},
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{
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.name = "uart1",
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.pins = uart1_pins,
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.npins = 5,
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},
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};
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#endif
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