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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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01f8fd7379
Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1459801503-15600-9-git-send-email-bp@alien8.de Signed-off-by: Ingo Molnar <mingo@kernel.org>
404 lines
11 KiB
C
404 lines
11 KiB
C
/*
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* x86 FPU boot time init code:
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*/
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#include <asm/fpu/internal.h>
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#include <asm/tlbflush.h>
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#include <asm/setup.h>
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#include <asm/cmdline.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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/*
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* Initialize the TS bit in CR0 according to the style of context-switches
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* we are using:
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*/
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static void fpu__init_cpu_ctx_switch(void)
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{
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if (!boot_cpu_has(X86_FEATURE_EAGER_FPU))
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stts();
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else
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clts();
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}
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/*
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* Initialize the registers found in all CPUs, CR0 and CR4:
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*/
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static void fpu__init_cpu_generic(void)
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{
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unsigned long cr0;
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unsigned long cr4_mask = 0;
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if (boot_cpu_has(X86_FEATURE_FXSR))
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cr4_mask |= X86_CR4_OSFXSR;
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if (boot_cpu_has(X86_FEATURE_XMM))
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cr4_mask |= X86_CR4_OSXMMEXCPT;
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if (cr4_mask)
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cr4_set_bits(cr4_mask);
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cr0 = read_cr0();
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cr0 &= ~(X86_CR0_TS|X86_CR0_EM); /* clear TS and EM */
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if (!boot_cpu_has(X86_FEATURE_FPU))
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cr0 |= X86_CR0_EM;
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write_cr0(cr0);
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/* Flush out any pending x87 state: */
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#ifdef CONFIG_MATH_EMULATION
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if (!boot_cpu_has(X86_FEATURE_FPU))
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fpstate_init_soft(¤t->thread.fpu.state.soft);
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else
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#endif
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asm volatile ("fninit");
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}
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/*
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* Enable all supported FPU features. Called when a CPU is brought online:
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*/
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void fpu__init_cpu(void)
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{
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fpu__init_cpu_generic();
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fpu__init_cpu_xstate();
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fpu__init_cpu_ctx_switch();
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}
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/*
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* The earliest FPU detection code.
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*
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* Set the X86_FEATURE_FPU CPU-capability bit based on
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* trying to execute an actual sequence of FPU instructions:
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*/
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static void fpu__init_system_early_generic(struct cpuinfo_x86 *c)
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{
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unsigned long cr0;
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u16 fsw, fcw;
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fsw = fcw = 0xffff;
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cr0 = read_cr0();
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cr0 &= ~(X86_CR0_TS | X86_CR0_EM);
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write_cr0(cr0);
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if (!test_bit(X86_FEATURE_FPU, (unsigned long *)cpu_caps_cleared)) {
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asm volatile("fninit ; fnstsw %0 ; fnstcw %1"
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: "+m" (fsw), "+m" (fcw));
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if (fsw == 0 && (fcw & 0x103f) == 0x003f)
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set_cpu_cap(c, X86_FEATURE_FPU);
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else
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clear_cpu_cap(c, X86_FEATURE_FPU);
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}
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#ifndef CONFIG_MATH_EMULATION
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if (!boot_cpu_has(X86_FEATURE_FPU)) {
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pr_emerg("x86/fpu: Giving up, no FPU found and no math emulation present\n");
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for (;;)
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asm volatile("hlt");
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}
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#endif
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}
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/*
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* Boot time FPU feature detection code:
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*/
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unsigned int mxcsr_feature_mask __read_mostly = 0xffffffffu;
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static void __init fpu__init_system_mxcsr(void)
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{
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unsigned int mask = 0;
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if (boot_cpu_has(X86_FEATURE_FXSR)) {
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/* Static because GCC does not get 16-byte stack alignment right: */
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static struct fxregs_state fxregs __initdata;
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asm volatile("fxsave %0" : "+m" (fxregs));
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mask = fxregs.mxcsr_mask;
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/*
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* If zero then use the default features mask,
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* which has all features set, except the
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* denormals-are-zero feature bit:
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*/
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if (mask == 0)
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mask = 0x0000ffbf;
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}
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mxcsr_feature_mask &= mask;
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}
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/*
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* Once per bootup FPU initialization sequences that will run on most x86 CPUs:
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*/
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static void __init fpu__init_system_generic(void)
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{
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/*
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* Set up the legacy init FPU context. (xstate init might overwrite this
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* with a more modern format, if the CPU supports it.)
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*/
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fpstate_init(&init_fpstate);
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fpu__init_system_mxcsr();
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}
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/*
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* Size of the FPU context state. All tasks in the system use the
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* same context size, regardless of what portion they use.
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* This is inherent to the XSAVE architecture which puts all state
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* components into a single, continuous memory block:
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*/
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unsigned int xstate_size;
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EXPORT_SYMBOL_GPL(xstate_size);
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/* Get alignment of the TYPE. */
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#define TYPE_ALIGN(TYPE) offsetof(struct { char x; TYPE test; }, test)
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/*
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* Enforce that 'MEMBER' is the last field of 'TYPE'.
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*
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* Align the computed size with alignment of the TYPE,
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* because that's how C aligns structs.
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*/
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#define CHECK_MEMBER_AT_END_OF(TYPE, MEMBER) \
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BUILD_BUG_ON(sizeof(TYPE) != ALIGN(offsetofend(TYPE, MEMBER), \
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TYPE_ALIGN(TYPE)))
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/*
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* We append the 'struct fpu' to the task_struct:
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*/
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static void __init fpu__init_task_struct_size(void)
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{
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int task_size = sizeof(struct task_struct);
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/*
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* Subtract off the static size of the register state.
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* It potentially has a bunch of padding.
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*/
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task_size -= sizeof(((struct task_struct *)0)->thread.fpu.state);
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/*
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* Add back the dynamically-calculated register state
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* size.
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*/
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task_size += xstate_size;
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/*
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* We dynamically size 'struct fpu', so we require that
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* it be at the end of 'thread_struct' and that
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* 'thread_struct' be at the end of 'task_struct'. If
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* you hit a compile error here, check the structure to
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* see if something got added to the end.
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*/
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CHECK_MEMBER_AT_END_OF(struct fpu, state);
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CHECK_MEMBER_AT_END_OF(struct thread_struct, fpu);
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CHECK_MEMBER_AT_END_OF(struct task_struct, thread);
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arch_task_struct_size = task_size;
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}
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/*
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* Set up the xstate_size based on the legacy FPU context size.
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*
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* We set this up first, and later it will be overwritten by
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* fpu__init_system_xstate() if the CPU knows about xstates.
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*/
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static void __init fpu__init_system_xstate_size_legacy(void)
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{
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static int on_boot_cpu __initdata = 1;
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WARN_ON_FPU(!on_boot_cpu);
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on_boot_cpu = 0;
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/*
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* Note that xstate_size might be overwriten later during
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* fpu__init_system_xstate().
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*/
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if (!boot_cpu_has(X86_FEATURE_FPU)) {
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/*
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* Disable xsave as we do not support it if i387
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* emulation is enabled.
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*/
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setup_clear_cpu_cap(X86_FEATURE_XSAVE);
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setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
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xstate_size = sizeof(struct swregs_state);
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} else {
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if (boot_cpu_has(X86_FEATURE_FXSR))
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xstate_size = sizeof(struct fxregs_state);
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else
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xstate_size = sizeof(struct fregs_state);
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}
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/*
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* Quirk: we don't yet handle the XSAVES* instructions
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* correctly, as we don't correctly convert between
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* standard and compacted format when interfacing
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* with user-space - so disable it for now.
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*
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* The difference is small: with recent CPUs the
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* compacted format is only marginally smaller than
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* the standard FPU state format.
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*
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* ( This is easy to backport while we are fixing
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* XSAVES* support. )
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*/
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setup_clear_cpu_cap(X86_FEATURE_XSAVES);
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}
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/*
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* FPU context switching strategies:
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*
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* Against popular belief, we don't do lazy FPU saves, due to the
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* task migration complications it brings on SMP - we only do
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* lazy FPU restores.
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*
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* 'lazy' is the traditional strategy, which is based on setting
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* CR0::TS to 1 during context-switch (instead of doing a full
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* restore of the FPU state), which causes the first FPU instruction
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* after the context switch (whenever it is executed) to fault - at
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* which point we lazily restore the FPU state into FPU registers.
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*
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* Tasks are of course under no obligation to execute FPU instructions,
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* so it can easily happen that another context-switch occurs without
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* a single FPU instruction being executed. If we eventually switch
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* back to the original task (that still owns the FPU) then we have
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* not only saved the restores along the way, but we also have the
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* FPU ready to be used for the original task.
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*
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* 'lazy' is deprecated because it's almost never a performance win
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* and it's much more complicated than 'eager'.
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*
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* 'eager' switching is by default on all CPUs, there we switch the FPU
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* state during every context switch, regardless of whether the task
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* has used FPU instructions in that time slice or not. This is done
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* because modern FPU context saving instructions are able to optimize
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* state saving and restoration in hardware: they can detect both
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* unused and untouched FPU state and optimize accordingly.
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*
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* [ Note that even in 'lazy' mode we might optimize context switches
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* to use 'eager' restores, if we detect that a task is using the FPU
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* frequently. See the fpu->counter logic in fpu/internal.h for that. ]
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*/
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static enum { ENABLE, DISABLE } eagerfpu = ENABLE;
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/*
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* Find supported xfeatures based on cpu features and command-line input.
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* This must be called after fpu__init_parse_early_param() is called and
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* xfeatures_mask is enumerated.
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*/
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u64 __init fpu__get_supported_xfeatures_mask(void)
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{
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/* Support all xfeatures known to us */
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if (eagerfpu != DISABLE)
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return XCNTXT_MASK;
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/* Warning of xfeatures being disabled for no eagerfpu mode */
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if (xfeatures_mask & XFEATURE_MASK_EAGER) {
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pr_err("x86/fpu: eagerfpu switching disabled, disabling the following xstate features: 0x%llx.\n",
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xfeatures_mask & XFEATURE_MASK_EAGER);
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}
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/* Return a mask that masks out all features requiring eagerfpu mode */
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return ~XFEATURE_MASK_EAGER;
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}
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/*
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* Disable features dependent on eagerfpu.
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*/
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static void __init fpu__clear_eager_fpu_features(void)
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{
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setup_clear_cpu_cap(X86_FEATURE_MPX);
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}
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/*
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* Pick the FPU context switching strategy:
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*
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* When eagerfpu is AUTO or ENABLE, we ensure it is ENABLE if either of
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* the following is true:
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*
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* (1) the cpu has xsaveopt, as it has the optimization and doing eager
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* FPU switching has a relatively low cost compared to a plain xsave;
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* (2) the cpu has xsave features (e.g. MPX) that depend on eager FPU
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* switching. Should the kernel boot with noxsaveopt, we support MPX
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* with eager FPU switching at a higher cost.
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*/
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static void __init fpu__init_system_ctx_switch(void)
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{
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static bool on_boot_cpu __initdata = 1;
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WARN_ON_FPU(!on_boot_cpu);
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on_boot_cpu = 0;
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WARN_ON_FPU(current->thread.fpu.fpstate_active);
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current_thread_info()->status = 0;
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if (boot_cpu_has(X86_FEATURE_XSAVEOPT) && eagerfpu != DISABLE)
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eagerfpu = ENABLE;
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if (xfeatures_mask & XFEATURE_MASK_EAGER)
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eagerfpu = ENABLE;
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if (eagerfpu == ENABLE)
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setup_force_cpu_cap(X86_FEATURE_EAGER_FPU);
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printk(KERN_INFO "x86/fpu: Using '%s' FPU context switches.\n", eagerfpu == ENABLE ? "eager" : "lazy");
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}
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/*
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* We parse fpu parameters early because fpu__init_system() is executed
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* before parse_early_param().
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*/
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static void __init fpu__init_parse_early_param(void)
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{
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if (cmdline_find_option_bool(boot_command_line, "eagerfpu=off")) {
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eagerfpu = DISABLE;
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fpu__clear_eager_fpu_features();
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}
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if (cmdline_find_option_bool(boot_command_line, "no387"))
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setup_clear_cpu_cap(X86_FEATURE_FPU);
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if (cmdline_find_option_bool(boot_command_line, "nofxsr")) {
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setup_clear_cpu_cap(X86_FEATURE_FXSR);
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setup_clear_cpu_cap(X86_FEATURE_FXSR_OPT);
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setup_clear_cpu_cap(X86_FEATURE_XMM);
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}
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if (cmdline_find_option_bool(boot_command_line, "noxsave"))
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fpu__xstate_clear_all_cpu_caps();
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if (cmdline_find_option_bool(boot_command_line, "noxsaveopt"))
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setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
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if (cmdline_find_option_bool(boot_command_line, "noxsaves"))
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setup_clear_cpu_cap(X86_FEATURE_XSAVES);
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}
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/*
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* Called on the boot CPU once per system bootup, to set up the initial
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* FPU state that is later cloned into all processes:
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*/
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void __init fpu__init_system(struct cpuinfo_x86 *c)
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{
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fpu__init_parse_early_param();
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fpu__init_system_early_generic(c);
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/*
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* The FPU has to be operational for some of the
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* later FPU init activities:
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*/
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fpu__init_cpu();
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/*
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* But don't leave CR0::TS set yet, as some of the FPU setup
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* methods depend on being able to execute FPU instructions
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* that will fault on a set TS, such as the FXSAVE in
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* fpu__init_system_mxcsr().
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*/
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clts();
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fpu__init_system_generic();
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fpu__init_system_xstate_size_legacy();
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fpu__init_system_xstate();
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fpu__init_task_struct_size();
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fpu__init_system_ctx_switch();
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}
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