mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-12 02:56:47 +07:00
6cd94d5e57
New and updated SoC support, notable changes include:
* bcm: brcmstb SMP support
* bcm: initial iproc/cygnus support
* exynos: Exynos4415 SoC support
* exynos: PMU and suspend support for Exynos5420
* exynos: PMU support for Exynos3250
* exynos: pm related maintenance
* imx: new LS1021A SoC support
* imx: vybrid 610 global timer support
* integrator: convert to using multiplatform configuration
* mediatek: earlyprintk support for mt8127/mt8135
* meson: meson8 soc and l2 cache controller support
* mvebu: Armada 38x CPU hotplug support
* mvebu: drop support for prerelease Armada 375 Z1 stepping
* mvebu: extended suspend support, now works on Armada 370/XP
* omap: hwmod related maintenance
* omap: prcm cleanup
* pxa: initial pxa27x DT handling
* rockchip: SMP support for rk3288
* rockchip: add cpu frequency scaling support
* shmobile: r8a7740 power domain support
* shmobile: various small restart, timer, pci apmu changes
* sunxi: Allwinner A80 (sun9i) earlyprintk support
* ux500: power domain support
Overall, a significant chunk of changes, coming mostly from
the usual suspects: omap, shmobile, samsung and mvebu, all of
which already contain a lot of platform specific code in
arch/arm.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIVAwUAVIcjyGCrR//JCVInAQJJCRAA1Tm+HZGiAiTvXEAcm/T9tIA08uqtawHt
cqyEAUyrnE8QxE4EhUd2pTw4EunVusqKF5EsDxOzw7b3ukUdLAWZE7bqBOSIJLqn
hrfsQQ8dXLbyC7T/CHPnBVeM+pn9LiIc9qzpZ0YToiMnHBBI4vKFQntBjd31yoRE
hN08I6AmDjQolOzzlqR1fuM0uZaKiHIcytdauTt3Vfqgg7FTHcTy3u1kClHTR1Lp
m/KuDothGpR5OKjSnUQz7EO5V3KJEnaKey8z2xM1a7DLLAvJ6r2+DUaDopv9Dbz1
W/V3H7fi5tLvillVa8xmlmzqWZbPc1xw8MWqvHZSWIMRZqloAHpC1VWKn0ZuH4SW
5Bj4ubSrpYjJxjKYfrxtjmuzru3A2jWBNTSP5A4nsny0C3AUsXkfRmRS0VNdegF8
sUdQ1MF8vEMpQT3QPH88+ccFHeIgqbcayhKqLPf7r8q0kwlym5N7Y2amU2A/O6qz
+324r+yzfSA70VgJZ5EhXxWVDOPB4Lc8EtoWnH6T/kjncIMwzEsbEbyB3X1OaREW
pVn3PNo06VjHLYoiHX+8G99pOFR/JZvaQs6jGCXLs+Orjp5WfP+kafkWqcB5GAKU
Pfd3AQsl6rKAITdu0XsTdPiICNS4CmBiWYPepQsTa3pQaNgB7fwZNQKelNRIdGc+
dF1lnQ7CXLQ=
=lFoH
-----END PGP SIGNATURE-----
Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Arnd Bergmann:
"New and updated SoC support, notable changes include:
- bcm:
brcmstb SMP support
initial iproc/cygnus support
- exynos:
Exynos4415 SoC support
PMU and suspend support for Exynos5420
PMU support for Exynos3250
pm related maintenance
- imx:
new LS1021A SoC support
vybrid 610 global timer support
- integrator:
convert to using multiplatform configuration
- mediatek:
earlyprintk support for mt8127/mt8135
- meson:
meson8 soc and l2 cache controller support
- mvebu:
Armada 38x CPU hotplug support
drop support for prerelease Armada 375 Z1 stepping
extended suspend support, now works on Armada 370/XP
- omap:
hwmod related maintenance
prcm cleanup
- pxa:
initial pxa27x DT handling
- rockchip:
SMP support for rk3288
add cpu frequency scaling support
- shmobile:
r8a7740 power domain support
various small restart, timer, pci apmu changes
- sunxi:
Allwinner A80 (sun9i) earlyprintk support
- ux500:
power domain support
Overall, a significant chunk of changes, coming mostly from the usual
suspects: omap, shmobile, samsung and mvebu, all of which already
contain a lot of platform specific code in arch/arm"
* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (187 commits)
ARM: mvebu: use the cpufreq-dt platform_data for independent clocks
soc: integrator: Add terminating entry for integrator_cm_match
ARM: mvebu: add SDRAM controller description for Armada XP
ARM: mvebu: adjust mbus controller description on Armada 370/XP
ARM: mvebu: add suspend/resume DT information for Armada XP GP
ARM: mvebu: synchronize secondary CPU clocks on resume
ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume
ARM: mvebu: Armada XP GP specific suspend/resume code
ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume
ARM: mvebu: implement suspend/resume support for Armada XP
clk: mvebu: add suspend/resume for gatable clocks
bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration
bus: mvebu-mbus: suspend/resume support
clocksource: time-armada-370-xp: add suspend/resume support
irqchip: armada-370-xp: Add suspend/resume support
ARM: add lolevel debug support for asm9260
ARM: add mach-asm9260
ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf
power: reset: imx-snvs-poweroff: add power off driver for i.mx6
ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A
...
110 lines
2.4 KiB
C
110 lines
2.4 KiB
C
/*
|
|
* Copyright 2014 Freescale Semiconductor, Inc.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#include <linux/irqchip.h>
|
|
#include <linux/of_platform.h>
|
|
#include <linux/phy.h>
|
|
#include <linux/regmap.h>
|
|
#include <linux/mfd/syscon.h>
|
|
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
|
|
#include <asm/mach/arch.h>
|
|
#include <asm/mach/map.h>
|
|
|
|
#include "common.h"
|
|
#include "cpuidle.h"
|
|
|
|
static int ar8031_phy_fixup(struct phy_device *dev)
|
|
{
|
|
u16 val;
|
|
|
|
/* Set RGMII IO voltage to 1.8V */
|
|
phy_write(dev, 0x1d, 0x1f);
|
|
phy_write(dev, 0x1e, 0x8);
|
|
|
|
/* introduce tx clock delay */
|
|
phy_write(dev, 0x1d, 0x5);
|
|
val = phy_read(dev, 0x1e);
|
|
val |= 0x0100;
|
|
phy_write(dev, 0x1e, val);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#define PHY_ID_AR8031 0x004dd074
|
|
static void __init imx6sx_enet_phy_init(void)
|
|
{
|
|
if (IS_BUILTIN(CONFIG_PHYLIB))
|
|
phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
|
|
ar8031_phy_fixup);
|
|
}
|
|
|
|
static void __init imx6sx_enet_clk_sel(void)
|
|
{
|
|
struct regmap *gpr;
|
|
|
|
gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sx-iomuxc-gpr");
|
|
if (!IS_ERR(gpr)) {
|
|
regmap_update_bits(gpr, IOMUXC_GPR1,
|
|
IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK, 0);
|
|
regmap_update_bits(gpr, IOMUXC_GPR1,
|
|
IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK, 0);
|
|
} else {
|
|
pr_err("failed to find fsl,imx6sx-iomux-gpr regmap\n");
|
|
}
|
|
}
|
|
|
|
static inline void imx6sx_enet_init(void)
|
|
{
|
|
imx6sx_enet_phy_init();
|
|
imx6sx_enet_clk_sel();
|
|
}
|
|
|
|
static void __init imx6sx_init_machine(void)
|
|
{
|
|
struct device *parent;
|
|
|
|
parent = imx_soc_device_init();
|
|
if (parent == NULL)
|
|
pr_warn("failed to initialize soc device\n");
|
|
|
|
of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
|
|
|
|
imx6sx_enet_init();
|
|
imx_anatop_init();
|
|
imx6sx_pm_init();
|
|
}
|
|
|
|
static void __init imx6sx_init_irq(void)
|
|
{
|
|
imx_init_revision_from_anatop();
|
|
imx_init_l2cache();
|
|
imx_src_init();
|
|
imx_gpc_init();
|
|
irqchip_init();
|
|
}
|
|
|
|
static void __init imx6sx_init_late(void)
|
|
{
|
|
imx6q_cpuidle_init();
|
|
|
|
if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
|
|
platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
|
|
}
|
|
|
|
static const char * const imx6sx_dt_compat[] __initconst = {
|
|
"fsl,imx6sx",
|
|
NULL,
|
|
};
|
|
|
|
DT_MACHINE_START(IMX6SX, "Freescale i.MX6 SoloX (Device Tree)")
|
|
.init_irq = imx6sx_init_irq,
|
|
.init_machine = imx6sx_init_machine,
|
|
.dt_compat = imx6sx_dt_compat,
|
|
.init_late = imx6sx_init_late,
|
|
MACHINE_END
|