Will Deacon 01d57485fc arm64: tlbflush: Ensure start/end of address range are aligned to stride ... Since commit 3d65b6bbc0 ("arm64: tlbi: Set MAX_TLBI_OPS to PTRS_PER_PTE"), we resort to per-ASID invalidation when attempting to perform more than PTRS_PER_PTE invalidation instructions in a single call to __flush_tlb_range(). Whilst this is beneficial, the mmu_gather code does not ensure that the end address of the range is rounded-up to the stride when freeing intermediate page tables in pXX_free_tlb(), which defeats our range checking. Align the bounds passed into __flush_tlb_range(). Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Peter Zijlstra <peterz@infradead.org> Reported-by: Hanjun Guo <guohanjun@huawei.com> Tested-by: Hanjun Guo <guohanjun@huawei.com> Reviewed-by: Hanjun Guo <guohanjun@huawei.com> Signed-off-by: Will Deacon <will.deacon@arm.com>		2019-06-12 16:19:45 +01:00
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asm	arm64: tlbflush: Ensure start/end of address range are aligned to stride	2019-06-12 16:19:45 +01:00
uapi/asm	* ARM: support for SVE and Pointer Authentication in guests, PMU improvements	2019-05-17 10:33:30 -07:00