mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-14 16:16:41 +07:00
8430305dc3
move mmp2 clock definition to another file. Then mmp2 can choose common clock framework or private clock framework. Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
112 lines
3.4 KiB
C
112 lines
3.4 KiB
C
#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <mach/addr-map.h>
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#include "common.h"
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#include "clock.h"
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/*
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* APB Clock register offsets for MMP2
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*/
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#define APBC_RTC APBC_REG(0x000)
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#define APBC_TWSI1 APBC_REG(0x004)
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#define APBC_TWSI2 APBC_REG(0x008)
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#define APBC_TWSI3 APBC_REG(0x00c)
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#define APBC_TWSI4 APBC_REG(0x010)
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#define APBC_KPC APBC_REG(0x018)
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#define APBC_UART1 APBC_REG(0x02c)
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#define APBC_UART2 APBC_REG(0x030)
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#define APBC_UART3 APBC_REG(0x034)
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#define APBC_GPIO APBC_REG(0x038)
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#define APBC_PWM0 APBC_REG(0x03c)
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#define APBC_PWM1 APBC_REG(0x040)
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#define APBC_PWM2 APBC_REG(0x044)
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#define APBC_PWM3 APBC_REG(0x048)
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#define APBC_SSP0 APBC_REG(0x04c)
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#define APBC_SSP1 APBC_REG(0x050)
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#define APBC_SSP2 APBC_REG(0x054)
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#define APBC_SSP3 APBC_REG(0x058)
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#define APBC_SSP4 APBC_REG(0x05c)
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#define APBC_SSP5 APBC_REG(0x060)
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#define APBC_TWSI5 APBC_REG(0x07c)
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#define APBC_TWSI6 APBC_REG(0x080)
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#define APBC_UART4 APBC_REG(0x088)
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#define APMU_USB APMU_REG(0x05c)
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#define APMU_NAND APMU_REG(0x060)
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#define APMU_SDH0 APMU_REG(0x054)
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#define APMU_SDH1 APMU_REG(0x058)
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#define APMU_SDH2 APMU_REG(0x0e8)
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#define APMU_SDH3 APMU_REG(0x0ec)
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static void sdhc_clk_enable(struct clk *clk)
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{
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uint32_t clk_rst;
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clk_rst = __raw_readl(clk->clk_rst);
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clk_rst |= clk->enable_val;
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__raw_writel(clk_rst, clk->clk_rst);
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}
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static void sdhc_clk_disable(struct clk *clk)
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{
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uint32_t clk_rst;
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clk_rst = __raw_readl(clk->clk_rst);
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clk_rst &= ~clk->enable_val;
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__raw_writel(clk_rst, clk->clk_rst);
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}
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struct clkops sdhc_clk_ops = {
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.enable = sdhc_clk_enable,
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.disable = sdhc_clk_disable,
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};
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/* APB peripheral clocks */
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static APBC_CLK(uart1, UART1, 1, 26000000);
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static APBC_CLK(uart2, UART2, 1, 26000000);
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static APBC_CLK(uart3, UART3, 1, 26000000);
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static APBC_CLK(uart4, UART4, 1, 26000000);
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static APBC_CLK(twsi1, TWSI1, 0, 26000000);
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static APBC_CLK(twsi2, TWSI2, 0, 26000000);
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static APBC_CLK(twsi3, TWSI3, 0, 26000000);
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static APBC_CLK(twsi4, TWSI4, 0, 26000000);
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static APBC_CLK(twsi5, TWSI5, 0, 26000000);
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static APBC_CLK(twsi6, TWSI6, 0, 26000000);
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static APBC_CLK(gpio, GPIO, 0, 26000000);
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static APMU_CLK(nand, NAND, 0xbf, 100000000);
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static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
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static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
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static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
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static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
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static struct clk_lookup mmp2_clkregs[] = {
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INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
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INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
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INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
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INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL),
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INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL),
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INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL),
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INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL),
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INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL),
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INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
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INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
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INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
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INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
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INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
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INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
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INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
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INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"),
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};
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void __init mmp2_clk_init(void)
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{
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clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs));
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}
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