mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
ed780686de
Just as the 32-bit contents, the 64-bit device tree branch also contains
a number of additions this release cycle.
New platforms:
- LG LG1313
- Mediatek MT6755
- Renesas r8a7796
- Broadcom 2837
Other platforms with larger updates are:
- Nvidia X1 platforms (USB 3.0, regulators, display subsystem)
- Mediatek MT8173 (display subsystem added)
- Rockchip RK3399 (a lot of new peripherals)
- ARM Juno reference implementation (SCPI power domains, coresight, thermal)
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Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull 64-bit ARM DT updates from Olof Johansson:
"Just as the 32-bit contents, the 64-bit device tree branch also
contains a number of additions this release cycle.
New platforms:
- LG LG1313
- Mediatek MT6755
- Renesas r8a7796
- Broadcom 2837
Other platforms with larger updates are:
- Nvidia X1 platforms (USB 3.0, regulators, display subsystem)
- Mediatek MT8173 (display subsystem added)
- Rockchip RK3399 (a lot of new peripherals)
- ARM Juno reference implementation (SCPI power domains, coresight,
thermal)"
* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (118 commits)
arm64: tegra: Enable HDMI on Jetson TX1
arm64: tegra: Add sor1_src clock
arm64: tegra: Add XUSB powergates on Tegra210
arm64: tegra: Add DPAUX pinctrl bindings
arm64: tegra: Add ACONNECT bus node for Tegra210
arm64: tegra: Add audio powergate node for Tegra210
arm64: tegra: Add regulators for Tegra210 Smaug
arm64: tegra: Correct Tegra210 XUSB mailbox interrupt
arm64: tegra: Enable XUSB controller on Jetson TX1
arm64: tegra: Enable debug serial on Jetson TX1
arm64: tegra: Add Tegra210 XUSB controller
arm64: tegra: Add Tegra210 XUSB pad controller
arm64: tegra: Add DSI panel on Jetson TX1
arm64: tegra: p2597: Add SDMMC power supplies
arm64: tegra: Add PMIC support on Jetson TX1
Revert "ARM64: DTS: meson-gxbb: switch ethernet to real clock"
arm64: dts: hi6220: Add pl031 RTC support
arm64: dts: r8a7796/salvator-x: Enable watchdog timer
arm64: dts: r8a7796: Add RWDT node
arm64: dts: r8a7796: Use SYSC "always-on" PM Domain
...
562 lines
15 KiB
Plaintext
562 lines
15 KiB
Plaintext
/*
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* BSD LICENSE
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*
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* Copyright (c) 2015 Broadcom. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Broadcom Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/bcm-ns2.h>
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/ {
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compatible = "brcm,ns2";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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A57_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0 0>;
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enable-method = "psci";
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next-level-cache = <&CLUSTER0_L2>;
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};
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A57_1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0 1>;
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enable-method = "psci";
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next-level-cache = <&CLUSTER0_L2>;
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};
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A57_2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0 2>;
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enable-method = "psci";
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next-level-cache = <&CLUSTER0_L2>;
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};
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A57_3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0 3>;
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enable-method = "psci";
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next-level-cache = <&CLUSTER0_L2>;
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};
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CLUSTER0_L2: l2-cache@000 {
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compatible = "cache";
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
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IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
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IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
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IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
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IRQ_TYPE_EDGE_RISING)>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&A57_0>,
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<&A57_1>,
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<&A57_2>,
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<&A57_3>;
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};
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pcie0: pcie@20020000 {
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compatible = "brcm,iproc-pcie";
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reg = <0 0x20020000 0 0x1000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 281 IRQ_TYPE_NONE>;
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linux,pci-domain = <0>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
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brcm,pcie-ob;
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brcm,pcie-ob-oarr-size;
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brcm,pcie-ob-axi-offset = <0x00000000>;
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brcm,pcie-ob-window-size = <256>;
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status = "disabled";
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msi-parent = <&msi0>;
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msi0: msi@20020000 {
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compatible = "brcm,iproc-msi";
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msi-controller;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 277 IRQ_TYPE_NONE>,
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<GIC_SPI 278 IRQ_TYPE_NONE>,
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<GIC_SPI 279 IRQ_TYPE_NONE>,
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<GIC_SPI 280 IRQ_TYPE_NONE>;
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brcm,num-eq-region = <1>;
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brcm,num-msi-msg-region = <1>;
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};
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};
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pcie4: pcie@50020000 {
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compatible = "brcm,iproc-pcie";
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reg = <0 0x50020000 0 0x1000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 305 IRQ_TYPE_NONE>;
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linux,pci-domain = <4>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
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brcm,pcie-ob;
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brcm,pcie-ob-oarr-size;
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brcm,pcie-ob-axi-offset = <0x30000000>;
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brcm,pcie-ob-window-size = <256>;
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status = "disabled";
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msi-parent = <&msi4>;
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msi4: msi@50020000 {
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compatible = "brcm,iproc-msi";
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msi-controller;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 301 IRQ_TYPE_NONE>,
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<GIC_SPI 302 IRQ_TYPE_NONE>,
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<GIC_SPI 303 IRQ_TYPE_NONE>,
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<GIC_SPI 304 IRQ_TYPE_NONE>;
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};
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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#include "ns2-clock.dtsi"
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dma0: dma@61360000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x61360000 0x1000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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clocks = <&iprocslow>;
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clock-names = "apb_pclk";
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};
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smmu: mmu@64000000 {
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compatible = "arm,mmu-500";
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reg = <0x64000000 0x40000>;
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#global-interrupts = <2>;
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interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
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mmu-masters;
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};
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pinctrl: pinctrl@6501d130 {
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compatible = "brcm,ns2-pinmux";
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reg = <0x6501d130 0x08>,
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<0x660a0028 0x04>,
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<0x660009b0 0x40>;
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};
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gpio_aon: gpio@65024800 {
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compatible = "brcm,iproc-gpio";
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reg = <0x65024800 0x50>,
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<0x65024008 0x18>;
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ngpios = <6>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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gic: interrupt-controller@65210000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x65210000 0x1000>,
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<0x65220000 0x1000>,
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<0x65240000 0x2000>,
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<0x65260000 0x1000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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cci@65590000 {
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compatible = "arm,cci-400";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x65590000 0x1000>;
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ranges = <0 0x65590000 0x10000>;
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pmu@9000 {
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compatible = "arm,cci-400-pmu,r1",
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"arm,cci-400-pmu";
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reg = <0x9000 0x4000>;
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interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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mdio_mux_iproc: mdio-mux@6602023c {
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compatible = "brcm,mdio-mux-iproc";
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reg = <0x6602023c 0x14>;
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#address-cells = <1>;
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#size-cells = <0>;
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mdio@0 {
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reg = <0x0>;
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#address-cells = <1>;
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#size-cells = <0>;
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pci_phy0: pci-phy@0 {
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compatible = "brcm,ns2-pcie-phy";
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reg = <0x0>;
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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mdio@7 {
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reg = <0x7>;
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#address-cells = <1>;
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#size-cells = <0>;
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pci_phy1: pci-phy@0 {
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compatible = "brcm,ns2-pcie-phy";
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reg = <0x0>;
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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mdio@10 {
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reg = <0x10>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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timer0: timer@66030000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x66030000 0x1000>;
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interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>,
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<&iprocslow>,
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<&iprocslow>;
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clock-names = "timer1", "timer2", "apb_pclk";
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};
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timer1: timer@66040000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x66040000 0x1000>;
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interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>,
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<&iprocslow>,
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<&iprocslow>;
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clock-names = "timer1", "timer2", "apb_pclk";
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};
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timer2: timer@66050000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x66050000 0x1000>;
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interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>,
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<&iprocslow>,
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<&iprocslow>;
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clock-names = "timer1", "timer2", "apb_pclk";
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};
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timer3: timer@66060000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x66060000 0x1000>;
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interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>,
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<&iprocslow>,
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<&iprocslow>;
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clock-names = "timer1", "timer2", "apb_pclk";
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};
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i2c0: i2c@66080000 {
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compatible = "brcm,iproc-i2c";
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reg = <0x66080000 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 394 IRQ_TYPE_NONE>;
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|
clock-frequency = <100000>;
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status = "disabled";
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};
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|
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wdt0: watchdog@66090000 {
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compatible = "arm,sp805", "arm,primecell";
|
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reg = <0x66090000 0x1000>;
|
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interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&iprocslow>, <&iprocslow>;
|
|
clock-names = "wdogclk", "apb_pclk";
|
|
};
|
|
|
|
gpio_g: gpio@660a0000 {
|
|
compatible = "brcm,iproc-gpio";
|
|
reg = <0x660a0000 0x50>;
|
|
ngpios = <32>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
i2c1: i2c@660b0000 {
|
|
compatible = "brcm,iproc-i2c";
|
|
reg = <0x660b0000 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 395 IRQ_TYPE_NONE>;
|
|
clock-frequency = <100000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart0: serial@66100000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x66100000 0x100>;
|
|
interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&iprocslow>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@66110000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x66110000 0x100>;
|
|
interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&iprocslow>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@66120000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x66120000 0x100>;
|
|
interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&iprocslow>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@66130000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x66130000 0x100>;
|
|
interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&osc>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ssp0: ssp@66180000 {
|
|
compatible = "arm,pl022", "arm,primecell";
|
|
reg = <0x66180000 0x1000>;
|
|
interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&iprocslow>, <&iprocslow>;
|
|
clock-names = "spiclk", "apb_pclk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ssp1: ssp@66190000 {
|
|
compatible = "arm,pl022", "arm,primecell";
|
|
reg = <0x66190000 0x1000>;
|
|
interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&iprocslow>, <&iprocslow>;
|
|
clock-names = "spiclk", "apb_pclk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hwrng: hwrng@66220000 {
|
|
compatible = "brcm,iproc-rng200";
|
|
reg = <0x66220000 0x28>;
|
|
};
|
|
|
|
sata_phy: sata_phy@663f0100 {
|
|
compatible = "brcm,iproc-ns2-sata-phy";
|
|
reg = <0x663f0100 0x1f00>,
|
|
<0x663f004c 0x10>;
|
|
reg-names = "phy", "phy-ctrl";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
sata_phy0: sata-phy@0 {
|
|
reg = <0>;
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sata_phy1: sata-phy@1 {
|
|
reg = <1>;
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
sata: ahci@663f2000 {
|
|
compatible = "brcm,iproc-ahci", "generic-ahci";
|
|
reg = <0x663f2000 0x1000>;
|
|
reg-names = "ahci";
|
|
interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
sata0: sata-port@0 {
|
|
reg = <0>;
|
|
phys = <&sata_phy0>;
|
|
phy-names = "sata-phy";
|
|
};
|
|
|
|
sata1: sata-port@1 {
|
|
reg = <1>;
|
|
phys = <&sata_phy1>;
|
|
phy-names = "sata-phy";
|
|
};
|
|
};
|
|
|
|
sdio0: sdhci@66420000 {
|
|
compatible = "brcm,sdhci-iproc-cygnus";
|
|
reg = <0x66420000 0x100>;
|
|
interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-width = <8>;
|
|
clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdio1: sdhci@66430000 {
|
|
compatible = "brcm,sdhci-iproc-cygnus";
|
|
reg = <0x66430000 0x100>;
|
|
interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-width = <8>;
|
|
clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
nand: nand@66460000 {
|
|
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
|
|
reg = <0x66460000 0x600>,
|
|
<0x67015408 0x600>,
|
|
<0x66460f00 0x20>;
|
|
reg-names = "nand", "iproc-idm", "iproc-ext";
|
|
interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
brcm,nand-has-wp;
|
|
};
|
|
};
|
|
};
|