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516eca2726
The defines and typedefs (hw_interrupt_type, no_irq_type, irq_desc_t) have been kept around for migration reasons. After more than two years it's time to remove them finally. This patch cleans up one of the remaining users. When all such patches hit mainline we can remove the defines and typedefs finally. Impact: cleanup Convert the last remaining users and remove the typedef. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
766 lines
19 KiB
C
766 lines
19 KiB
C
/*
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* twl4030-irq.c - TWL4030/TPS659x0 irq support
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*
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* Copyright (C) 2005-2006 Texas Instruments, Inc.
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*
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* Modifications to defer interrupt handling to a kernel thread:
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* Copyright (C) 2006 MontaVista Software, Inc.
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*
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* Based on tlv320aic23.c:
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* Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
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*
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* Code cleanup and modifications to IRQ handler.
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* by syed khasim <x0khasim@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kthread.h>
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#include <linux/i2c/twl4030.h>
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/*
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* TWL4030 IRQ handling has two stages in hardware, and thus in software.
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* The Primary Interrupt Handler (PIH) stage exposes status bits saying
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* which Secondary Interrupt Handler (SIH) stage is raising an interrupt.
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* SIH modules are more traditional IRQ components, which support per-IRQ
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* enable/disable and trigger controls; they do most of the work.
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*
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* These chips are designed to support IRQ handling from two different
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* I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status
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* and mask registers in the PIH and SIH modules.
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*
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* We set up IRQs starting at a platform-specified base, always starting
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* with PIH and the SIH for PWR_INT and then usually adding GPIO:
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* base + 0 .. base + 7 PIH
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* base + 8 .. base + 15 SIH for PWR_INT
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* base + 16 .. base + 33 SIH for GPIO
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*/
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/* PIH register offsets */
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#define REG_PIH_ISR_P1 0x01
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#define REG_PIH_ISR_P2 0x02
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#define REG_PIH_SIR 0x03 /* for testing */
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/* Linux could (eventually) use either IRQ line */
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static int irq_line;
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struct sih {
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char name[8];
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u8 module; /* module id */
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u8 control_offset; /* for SIH_CTRL */
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bool set_cor;
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u8 bits; /* valid in isr/imr */
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u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */
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u8 edr_offset;
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u8 bytes_edr; /* bytelen of EDR */
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/* SIR ignored -- set interrupt, for testing only */
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struct irq_data {
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u8 isr_offset;
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u8 imr_offset;
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} mask[2];
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/* + 2 bytes padding */
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};
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#define SIH_INITIALIZER(modname, nbits) \
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.module = TWL4030_MODULE_ ## modname, \
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.control_offset = TWL4030_ ## modname ## _SIH_CTRL, \
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.bits = nbits, \
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.bytes_ixr = DIV_ROUND_UP(nbits, 8), \
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.edr_offset = TWL4030_ ## modname ## _EDR, \
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.bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \
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.mask = { { \
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.isr_offset = TWL4030_ ## modname ## _ISR1, \
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.imr_offset = TWL4030_ ## modname ## _IMR1, \
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}, \
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{ \
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.isr_offset = TWL4030_ ## modname ## _ISR2, \
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.imr_offset = TWL4030_ ## modname ## _IMR2, \
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}, },
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/* register naming policies are inconsistent ... */
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#define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1
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#define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD
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#define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT
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/* Order in this table matches order in PIH_ISR. That is,
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* BIT(n) in PIH_ISR is sih_modules[n].
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*/
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static const struct sih sih_modules[6] = {
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[0] = {
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.name = "gpio",
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.module = TWL4030_MODULE_GPIO,
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.control_offset = REG_GPIO_SIH_CTRL,
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.set_cor = true,
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.bits = TWL4030_GPIO_MAX,
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.bytes_ixr = 3,
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/* Note: *all* of these IRQs default to no-trigger */
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.edr_offset = REG_GPIO_EDR1,
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.bytes_edr = 5,
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.mask = { {
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.isr_offset = REG_GPIO_ISR1A,
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.imr_offset = REG_GPIO_IMR1A,
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}, {
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.isr_offset = REG_GPIO_ISR1B,
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.imr_offset = REG_GPIO_IMR1B,
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}, },
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},
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[1] = {
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.name = "keypad",
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.set_cor = true,
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SIH_INITIALIZER(KEYPAD_KEYP, 4)
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},
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[2] = {
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.name = "bci",
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.module = TWL4030_MODULE_INTERRUPTS,
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.control_offset = TWL4030_INTERRUPTS_BCISIHCTRL,
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.bits = 12,
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.bytes_ixr = 2,
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.edr_offset = TWL4030_INTERRUPTS_BCIEDR1,
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/* Note: most of these IRQs default to no-trigger */
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.bytes_edr = 3,
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.mask = { {
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.isr_offset = TWL4030_INTERRUPTS_BCIISR1A,
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.imr_offset = TWL4030_INTERRUPTS_BCIIMR1A,
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}, {
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.isr_offset = TWL4030_INTERRUPTS_BCIISR1B,
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.imr_offset = TWL4030_INTERRUPTS_BCIIMR1B,
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}, },
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},
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[3] = {
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.name = "madc",
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SIH_INITIALIZER(MADC, 4)
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},
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[4] = {
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/* USB doesn't use the same SIH organization */
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.name = "usb",
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},
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[5] = {
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.name = "power",
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.set_cor = true,
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SIH_INITIALIZER(INT_PWR, 8)
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},
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/* there are no SIH modules #6 or #7 ... */
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};
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#undef TWL4030_MODULE_KEYPAD_KEYP
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#undef TWL4030_MODULE_INT_PWR
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#undef TWL4030_INT_PWR_EDR
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/*----------------------------------------------------------------------*/
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static unsigned twl4030_irq_base;
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static struct completion irq_event;
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/*
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* This thread processes interrupts reported by the Primary Interrupt Handler.
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*/
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static int twl4030_irq_thread(void *data)
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{
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long irq = (long)data;
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struct irq_desc *desc = irq_to_desc(irq);
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static unsigned i2c_errors;
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static const unsigned max_i2c_errors = 100;
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if (!desc) {
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pr_err("twl4030: Invalid IRQ: %ld\n", irq);
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return -EINVAL;
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}
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current->flags |= PF_NOFREEZE;
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while (!kthread_should_stop()) {
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int ret;
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int module_irq;
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u8 pih_isr;
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/* Wait for IRQ, then read PIH irq status (also blocking) */
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wait_for_completion_interruptible(&irq_event);
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ret = twl4030_i2c_read_u8(TWL4030_MODULE_PIH, &pih_isr,
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REG_PIH_ISR_P1);
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if (ret) {
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pr_warning("twl4030: I2C error %d reading PIH ISR\n",
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ret);
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if (++i2c_errors >= max_i2c_errors) {
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printk(KERN_ERR "Maximum I2C error count"
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" exceeded. Terminating %s.\n",
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__func__);
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break;
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}
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complete(&irq_event);
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continue;
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}
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/* these handlers deal with the relevant SIH irq status */
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local_irq_disable();
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for (module_irq = twl4030_irq_base;
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pih_isr;
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pih_isr >>= 1, module_irq++) {
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if (pih_isr & 0x1) {
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struct irq_desc *d = irq_to_desc(module_irq);
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if (!d) {
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pr_err("twl4030: Invalid SIH IRQ: %d\n",
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module_irq);
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return -EINVAL;
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}
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/* These can't be masked ... always warn
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* if we get any surprises.
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*/
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if (d->status & IRQ_DISABLED)
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note_interrupt(module_irq, d,
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IRQ_NONE);
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else
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d->handle_irq(module_irq, d);
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}
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}
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local_irq_enable();
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desc->chip->unmask(irq);
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}
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return 0;
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}
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/*
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* handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt.
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* This is a chained interrupt, so there is no desc->action method for it.
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* Now we need to query the interrupt controller in the twl4030 to determine
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* which module is generating the interrupt request. However, we can't do i2c
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* transactions in interrupt context, so we must defer that work to a kernel
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* thread. All we do here is acknowledge and mask the interrupt and wakeup
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* the kernel thread.
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*/
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static void handle_twl4030_pih(unsigned int irq, struct irq_desc *desc)
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{
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/* Acknowledge, clear *AND* mask the interrupt... */
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desc->chip->ack(irq);
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complete(&irq_event);
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}
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static struct task_struct *start_twl4030_irq_thread(long irq)
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{
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struct task_struct *thread;
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init_completion(&irq_event);
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thread = kthread_run(twl4030_irq_thread, (void *)irq, "twl4030-irq");
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if (!thread)
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pr_err("twl4030: could not create irq %ld thread!\n", irq);
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return thread;
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}
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/*----------------------------------------------------------------------*/
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/*
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* twl4030_init_sih_modules() ... start from a known state where no
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* IRQs will be coming in, and where we can quickly enable them then
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* handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL.
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*
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* NOTE: we don't touch EDR registers here; they stay with hardware
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* defaults or whatever the last value was. Note that when both EDR
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* bits for an IRQ are clear, that's as if its IMR bit is set...
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*/
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static int twl4030_init_sih_modules(unsigned line)
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{
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const struct sih *sih;
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u8 buf[4];
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int i;
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int status;
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/* line 0 == int1_n signal; line 1 == int2_n signal */
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if (line > 1)
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return -EINVAL;
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irq_line = line;
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/* disable all interrupts on our line */
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memset(buf, 0xff, sizeof buf);
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sih = sih_modules;
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for (i = 0; i < ARRAY_SIZE(sih_modules); i++, sih++) {
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/* skip USB -- it's funky */
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if (!sih->bytes_ixr)
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continue;
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status = twl4030_i2c_write(sih->module, buf,
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sih->mask[line].imr_offset, sih->bytes_ixr);
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if (status < 0)
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pr_err("twl4030: err %d initializing %s %s\n",
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status, sih->name, "IMR");
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/* Maybe disable "exclusive" mode; buffer second pending irq;
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* set Clear-On-Read (COR) bit.
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*
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* NOTE that sometimes COR polarity is documented as being
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* inverted: for MADC and BCI, COR=1 means "clear on write".
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* And for PWR_INT it's not documented...
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*/
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if (sih->set_cor) {
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status = twl4030_i2c_write_u8(sih->module,
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TWL4030_SIH_CTRL_COR_MASK,
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sih->control_offset);
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if (status < 0)
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pr_err("twl4030: err %d initializing %s %s\n",
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status, sih->name, "SIH_CTRL");
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}
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}
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sih = sih_modules;
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for (i = 0; i < ARRAY_SIZE(sih_modules); i++, sih++) {
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u8 rxbuf[4];
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int j;
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/* skip USB */
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if (!sih->bytes_ixr)
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continue;
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/* Clear pending interrupt status. Either the read was
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* enough, or we need to write those bits. Repeat, in
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* case an IRQ is pending (PENDDIS=0) ... that's not
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* uncommon with PWR_INT.PWRON.
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*/
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for (j = 0; j < 2; j++) {
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status = twl4030_i2c_read(sih->module, rxbuf,
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sih->mask[line].isr_offset, sih->bytes_ixr);
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if (status < 0)
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pr_err("twl4030: err %d initializing %s %s\n",
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status, sih->name, "ISR");
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if (!sih->set_cor)
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status = twl4030_i2c_write(sih->module, buf,
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sih->mask[line].isr_offset,
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sih->bytes_ixr);
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/* else COR=1 means read sufficed.
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* (for most SIH modules...)
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*/
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}
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}
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return 0;
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}
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static inline void activate_irq(int irq)
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{
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#ifdef CONFIG_ARM
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/* ARM requires an extra step to clear IRQ_NOREQUEST, which it
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* sets on behalf of every irq_chip. Also sets IRQ_NOPROBE.
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*/
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set_irq_flags(irq, IRQF_VALID);
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#else
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/* same effect on other architectures */
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set_irq_noprobe(irq);
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#endif
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}
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/*----------------------------------------------------------------------*/
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static DEFINE_SPINLOCK(sih_agent_lock);
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static struct workqueue_struct *wq;
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struct sih_agent {
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int irq_base;
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const struct sih *sih;
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u32 imr;
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bool imr_change_pending;
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struct work_struct mask_work;
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u32 edge_change;
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struct work_struct edge_work;
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};
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static void twl4030_sih_do_mask(struct work_struct *work)
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{
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struct sih_agent *agent;
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const struct sih *sih;
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union {
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u8 bytes[4];
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u32 word;
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} imr;
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int status;
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agent = container_of(work, struct sih_agent, mask_work);
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/* see what work we have */
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spin_lock_irq(&sih_agent_lock);
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if (agent->imr_change_pending) {
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sih = agent->sih;
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/* byte[0] gets overwritten as we write ... */
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imr.word = cpu_to_le32(agent->imr << 8);
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agent->imr_change_pending = false;
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} else
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sih = NULL;
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spin_unlock_irq(&sih_agent_lock);
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if (!sih)
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return;
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/* write the whole mask ... simpler than subsetting it */
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status = twl4030_i2c_write(sih->module, imr.bytes,
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sih->mask[irq_line].imr_offset, sih->bytes_ixr);
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if (status)
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pr_err("twl4030: %s, %s --> %d\n", __func__,
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"write", status);
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}
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static void twl4030_sih_do_edge(struct work_struct *work)
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{
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struct sih_agent *agent;
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const struct sih *sih;
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u8 bytes[6];
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u32 edge_change;
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int status;
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agent = container_of(work, struct sih_agent, edge_work);
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/* see what work we have */
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spin_lock_irq(&sih_agent_lock);
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edge_change = agent->edge_change;
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agent->edge_change = 0;;
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sih = edge_change ? agent->sih : NULL;
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spin_unlock_irq(&sih_agent_lock);
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if (!sih)
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return;
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/* Read, reserving first byte for write scratch. Yes, this
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* could be cached for some speedup ... but be careful about
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* any processor on the other IRQ line, EDR registers are
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* shared.
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*/
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status = twl4030_i2c_read(sih->module, bytes + 1,
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sih->edr_offset, sih->bytes_edr);
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if (status) {
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pr_err("twl4030: %s, %s --> %d\n", __func__,
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"read", status);
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return;
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}
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/* Modify only the bits we know must change */
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while (edge_change) {
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int i = fls(edge_change) - 1;
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struct irq_desc *d = irq_to_desc(i + agent->irq_base);
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int byte = 1 + (i >> 2);
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int off = (i & 0x3) * 2;
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if (!d) {
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pr_err("twl4030: Invalid IRQ: %d\n",
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i + agent->irq_base);
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return;
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}
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bytes[byte] &= ~(0x03 << off);
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spin_lock_irq(&d->lock);
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if (d->status & IRQ_TYPE_EDGE_RISING)
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bytes[byte] |= BIT(off + 1);
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if (d->status & IRQ_TYPE_EDGE_FALLING)
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bytes[byte] |= BIT(off + 0);
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spin_unlock_irq(&d->lock);
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edge_change &= ~BIT(i);
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}
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/* Write */
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status = twl4030_i2c_write(sih->module, bytes,
|
|
sih->edr_offset, sih->bytes_edr);
|
|
if (status)
|
|
pr_err("twl4030: %s, %s --> %d\n", __func__,
|
|
"write", status);
|
|
}
|
|
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
/*
|
|
* All irq_chip methods get issued from code holding irq_desc[irq].lock,
|
|
* which can't perform the underlying I2C operations (because they sleep).
|
|
* So we must hand them off to a thread (workqueue) and cope with asynch
|
|
* completion, potentially including some re-ordering, of these requests.
|
|
*/
|
|
|
|
static void twl4030_sih_mask(unsigned irq)
|
|
{
|
|
struct sih_agent *sih = get_irq_chip_data(irq);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&sih_agent_lock, flags);
|
|
sih->imr |= BIT(irq - sih->irq_base);
|
|
sih->imr_change_pending = true;
|
|
queue_work(wq, &sih->mask_work);
|
|
spin_unlock_irqrestore(&sih_agent_lock, flags);
|
|
}
|
|
|
|
static void twl4030_sih_unmask(unsigned irq)
|
|
{
|
|
struct sih_agent *sih = get_irq_chip_data(irq);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&sih_agent_lock, flags);
|
|
sih->imr &= ~BIT(irq - sih->irq_base);
|
|
sih->imr_change_pending = true;
|
|
queue_work(wq, &sih->mask_work);
|
|
spin_unlock_irqrestore(&sih_agent_lock, flags);
|
|
}
|
|
|
|
static int twl4030_sih_set_type(unsigned irq, unsigned trigger)
|
|
{
|
|
struct sih_agent *sih = get_irq_chip_data(irq);
|
|
struct irq_desc *desc = irq_to_desc(irq);
|
|
unsigned long flags;
|
|
|
|
if (!desc) {
|
|
pr_err("twl4030: Invalid IRQ: %d\n", irq);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
|
|
return -EINVAL;
|
|
|
|
spin_lock_irqsave(&sih_agent_lock, flags);
|
|
if ((desc->status & IRQ_TYPE_SENSE_MASK) != trigger) {
|
|
desc->status &= ~IRQ_TYPE_SENSE_MASK;
|
|
desc->status |= trigger;
|
|
sih->edge_change |= BIT(irq - sih->irq_base);
|
|
queue_work(wq, &sih->edge_work);
|
|
}
|
|
spin_unlock_irqrestore(&sih_agent_lock, flags);
|
|
return 0;
|
|
}
|
|
|
|
static struct irq_chip twl4030_sih_irq_chip = {
|
|
.name = "twl4030",
|
|
.mask = twl4030_sih_mask,
|
|
.unmask = twl4030_sih_unmask,
|
|
.set_type = twl4030_sih_set_type,
|
|
};
|
|
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
static inline int sih_read_isr(const struct sih *sih)
|
|
{
|
|
int status;
|
|
union {
|
|
u8 bytes[4];
|
|
u32 word;
|
|
} isr;
|
|
|
|
/* FIXME need retry-on-error ... */
|
|
|
|
isr.word = 0;
|
|
status = twl4030_i2c_read(sih->module, isr.bytes,
|
|
sih->mask[irq_line].isr_offset, sih->bytes_ixr);
|
|
|
|
return (status < 0) ? status : le32_to_cpu(isr.word);
|
|
}
|
|
|
|
/*
|
|
* Generic handler for SIH interrupts ... we "know" this is called
|
|
* in task context, with IRQs enabled.
|
|
*/
|
|
static void handle_twl4030_sih(unsigned irq, struct irq_desc *desc)
|
|
{
|
|
struct sih_agent *agent = get_irq_data(irq);
|
|
const struct sih *sih = agent->sih;
|
|
int isr;
|
|
|
|
/* reading ISR acks the IRQs, using clear-on-read mode */
|
|
local_irq_enable();
|
|
isr = sih_read_isr(sih);
|
|
local_irq_disable();
|
|
|
|
if (isr < 0) {
|
|
pr_err("twl4030: %s SIH, read ISR error %d\n",
|
|
sih->name, isr);
|
|
/* REVISIT: recover; eventually mask it all, etc */
|
|
return;
|
|
}
|
|
|
|
while (isr) {
|
|
irq = fls(isr);
|
|
irq--;
|
|
isr &= ~BIT(irq);
|
|
|
|
if (irq < sih->bits)
|
|
generic_handle_irq(agent->irq_base + irq);
|
|
else
|
|
pr_err("twl4030: %s SIH, invalid ISR bit %d\n",
|
|
sih->name, irq);
|
|
}
|
|
}
|
|
|
|
static unsigned twl4030_irq_next;
|
|
|
|
/* returns the first IRQ used by this SIH bank,
|
|
* or negative errno
|
|
*/
|
|
int twl4030_sih_setup(int module)
|
|
{
|
|
int sih_mod;
|
|
const struct sih *sih = NULL;
|
|
struct sih_agent *agent;
|
|
int i, irq;
|
|
int status = -EINVAL;
|
|
unsigned irq_base = twl4030_irq_next;
|
|
|
|
/* only support modules with standard clear-on-read for now */
|
|
for (sih_mod = 0, sih = sih_modules;
|
|
sih_mod < ARRAY_SIZE(sih_modules);
|
|
sih_mod++, sih++) {
|
|
if (sih->module == module && sih->set_cor) {
|
|
if (!WARN((irq_base + sih->bits) > NR_IRQS,
|
|
"irq %d for %s too big\n",
|
|
irq_base + sih->bits,
|
|
sih->name))
|
|
status = 0;
|
|
break;
|
|
}
|
|
}
|
|
if (status < 0)
|
|
return status;
|
|
|
|
agent = kzalloc(sizeof *agent, GFP_KERNEL);
|
|
if (!agent)
|
|
return -ENOMEM;
|
|
|
|
status = 0;
|
|
|
|
agent->irq_base = irq_base;
|
|
agent->sih = sih;
|
|
agent->imr = ~0;
|
|
INIT_WORK(&agent->mask_work, twl4030_sih_do_mask);
|
|
INIT_WORK(&agent->edge_work, twl4030_sih_do_edge);
|
|
|
|
for (i = 0; i < sih->bits; i++) {
|
|
irq = irq_base + i;
|
|
|
|
set_irq_chip_and_handler(irq, &twl4030_sih_irq_chip,
|
|
handle_edge_irq);
|
|
set_irq_chip_data(irq, agent);
|
|
activate_irq(irq);
|
|
}
|
|
|
|
status = irq_base;
|
|
twl4030_irq_next += i;
|
|
|
|
/* replace generic PIH handler (handle_simple_irq) */
|
|
irq = sih_mod + twl4030_irq_base;
|
|
set_irq_data(irq, agent);
|
|
set_irq_chained_handler(irq, handle_twl4030_sih);
|
|
|
|
pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", sih->name,
|
|
irq, irq_base, twl4030_irq_next - 1);
|
|
|
|
return status;
|
|
}
|
|
|
|
/* FIXME need a call to reverse twl4030_sih_setup() ... */
|
|
|
|
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
/* FIXME pass in which interrupt line we'll use ... */
|
|
#define twl_irq_line 0
|
|
|
|
int twl_init_irq(int irq_num, unsigned irq_base, unsigned irq_end)
|
|
{
|
|
static struct irq_chip twl4030_irq_chip;
|
|
|
|
int status;
|
|
int i;
|
|
struct task_struct *task;
|
|
|
|
/*
|
|
* Mask and clear all TWL4030 interrupts since initially we do
|
|
* not have any TWL4030 module interrupt handlers present
|
|
*/
|
|
status = twl4030_init_sih_modules(twl_irq_line);
|
|
if (status < 0)
|
|
return status;
|
|
|
|
wq = create_singlethread_workqueue("twl4030-irqchip");
|
|
if (!wq) {
|
|
pr_err("twl4030: workqueue FAIL\n");
|
|
return -ESRCH;
|
|
}
|
|
|
|
twl4030_irq_base = irq_base;
|
|
|
|
/* install an irq handler for each of the SIH modules;
|
|
* clone dummy irq_chip since PIH can't *do* anything
|
|
*/
|
|
twl4030_irq_chip = dummy_irq_chip;
|
|
twl4030_irq_chip.name = "twl4030";
|
|
|
|
twl4030_sih_irq_chip.ack = dummy_irq_chip.ack;
|
|
|
|
for (i = irq_base; i < irq_end; i++) {
|
|
set_irq_chip_and_handler(i, &twl4030_irq_chip,
|
|
handle_simple_irq);
|
|
activate_irq(i);
|
|
}
|
|
twl4030_irq_next = i;
|
|
pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", "PIH",
|
|
irq_num, irq_base, twl4030_irq_next - 1);
|
|
|
|
/* ... and the PWR_INT module ... */
|
|
status = twl4030_sih_setup(TWL4030_MODULE_INT);
|
|
if (status < 0) {
|
|
pr_err("twl4030: sih_setup PWR INT --> %d\n", status);
|
|
goto fail;
|
|
}
|
|
|
|
/* install an irq handler to demultiplex the TWL4030 interrupt */
|
|
task = start_twl4030_irq_thread(irq_num);
|
|
if (!task) {
|
|
pr_err("twl4030: irq thread FAIL\n");
|
|
status = -ESRCH;
|
|
goto fail;
|
|
}
|
|
|
|
set_irq_data(irq_num, task);
|
|
set_irq_chained_handler(irq_num, handle_twl4030_pih);
|
|
|
|
return status;
|
|
|
|
fail:
|
|
for (i = irq_base; i < irq_end; i++)
|
|
set_irq_chip_and_handler(i, NULL, NULL);
|
|
destroy_workqueue(wq);
|
|
wq = NULL;
|
|
return status;
|
|
}
|
|
|
|
int twl_exit_irq(void)
|
|
{
|
|
/* FIXME undo twl_init_irq() */
|
|
if (twl4030_irq_base) {
|
|
pr_err("twl4030: can't yet clean up IRQs?\n");
|
|
return -ENOSYS;
|
|
}
|
|
return 0;
|
|
}
|