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013044cc65
Expose the CP0_EntryLo0 and CP0_EntryLo1 registers through the KVM register access API. This is fairly straightforward for trap & emulate since we don't support the RI and XI bits. For the sake of future proofing (particularly for VZ) it is explicitly specified that the API always exposes the 64-bit version of these registers (i.e. with the RI and XI bits in bit positions 63 and 62 respectively), and they are implemented in trap_emul.c rather than mips.c to allow them to be implemented differently for VZ. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org |
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| .. | ||
| arm | ||
| devices | ||
| 00-INDEX | ||
| api.txt | ||
| cpuid.txt | ||
| halt-polling.txt | ||
| hypercalls.txt | ||
| locking.txt | ||
| mmu.txt | ||
| msr.txt | ||
| nested-vmx.txt | ||
| ppc-pv.txt | ||
| review-checklist.txt | ||
| s390-diag.txt | ||
| timekeeping.txt | ||