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f1fe12c8bf
The Versatile Express was submitted with the actual display bridges unconnected (but defined in the device tree) and mock "panels" encoded in the device tree node of the PL111 controller. This doesn't even remotely describe the actual Versatile Express hardware. Exploit the SiI9022 bridge by connecting the PL111 pads to it, making it use EDID or fallback values to drive the monitor. The also has to use the reserved memory through the CMA pool rather than by open coding a memory region and remapping it explicitly in the driver. To achieve this, a reserved-memory node must exist in the root of the device tree, so we need to pull that out of the motherboard .dtsi include files, and push it into each top-level device tree instead. We do the same manouver for all the Versatile Express boards, taking into account the different location of the video RAM depending on which chip select is used on each platform. This plays nicely with the new PL111 DRM driver and follows the standard ways of assigning bridges and memory pools for graphics. Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Mali DP Maintainers <malidp@foss.arm.com> Cc: Robin Murphy <robin.murphy@arm.com> Tested-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
281 lines
6.0 KiB
Plaintext
281 lines
6.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* ARM Ltd. Versatile Express
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*
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* CoreTile Express A5x2
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* Cortex-A5 MPCore (V2P-CA5s)
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*
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* HBI-0225B
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*/
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/dts-v1/;
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#include "vexpress-v2m-rs1.dtsi"
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/ {
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model = "V2P-CA5s";
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arm,hbi = <0x225>;
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arm,vexpress,site = <0xf>;
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compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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chosen { };
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aliases {
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serial0 = &v2m_serial0;
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serial1 = &v2m_serial1;
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serial2 = &v2m_serial2;
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serial3 = &v2m_serial3;
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i2c0 = &v2m_i2c_dvi;
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i2c1 = &v2m_i2c_pcie;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x40000000>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* Chipselect 2 is physically at 0x18000000 */
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vram: vram@18000000 {
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/* 8 MB of designated video RAM */
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compatible = "shared-dma-pool";
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reg = <0x18000000 0x00800000>;
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no-map;
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};
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};
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hdlcd@2a110000 {
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compatible = "arm,hdlcd";
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reg = <0x2a110000 0x1000>;
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interrupts = <0 85 4>;
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clocks = <&hdlcd_clk>;
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clock-names = "pxlclk";
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};
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memory-controller@2a150000 {
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compatible = "arm,pl341", "arm,primecell";
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reg = <0x2a150000 0x1000>;
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clocks = <&axi_clk>;
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clock-names = "apb_pclk";
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};
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memory-controller@2a190000 {
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compatible = "arm,pl354", "arm,primecell";
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reg = <0x2a190000 0x1000>;
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interrupts = <0 86 4>,
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<0 87 4>;
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clocks = <&axi_clk>;
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clock-names = "apb_pclk";
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};
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scu@2c000000 {
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compatible = "arm,cortex-a5-scu";
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reg = <0x2c000000 0x58>;
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};
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timer@2c000600 {
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compatible = "arm,cortex-a5-twd-timer";
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reg = <0x2c000600 0x20>;
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interrupts = <1 13 0x304>;
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};
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timer@2c000200 {
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compatible = "arm,cortex-a5-global-timer",
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"arm,cortex-a9-global-timer";
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reg = <0x2c000200 0x20>;
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interrupts = <1 11 0x304>;
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clocks = <&cpu_clk>;
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};
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watchdog@2c000620 {
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compatible = "arm,cortex-a5-twd-wdt";
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reg = <0x2c000620 0x20>;
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interrupts = <1 14 0x304>;
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};
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gic: interrupt-controller@2c001000 {
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compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x2c001000 0x1000>,
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<0x2c000100 0x100>;
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};
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L2: cache-controller@2c0f0000 {
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compatible = "arm,pl310-cache";
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reg = <0x2c0f0000 0x1000>;
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interrupts = <0 84 4>;
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cache-level = <2>;
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};
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pmu {
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compatible = "arm,cortex-a5-pmu";
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interrupts = <0 68 4>,
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<0 69 4>;
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};
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dcc {
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compatible = "arm,vexpress,config-bus";
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arm,vexpress,config-bridge = <&v2m_sysreg>;
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cpu_clk: oscclk0 {
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/* CPU and internal AXI reference clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 0>;
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freq-range = <50000000 100000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk0";
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};
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axi_clk: oscclk1 {
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/* Multiplexed AXI master clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 1>;
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freq-range = <5000000 50000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk1";
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};
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oscclk2 {
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/* DDR2 */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 2>;
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freq-range = <80000000 120000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk2";
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};
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hdlcd_clk: oscclk3 {
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/* HDLCD */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 3>;
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freq-range = <23750000 165000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk3";
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};
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oscclk4 {
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/* Test chip gate configuration */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 4>;
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freq-range = <80000000 80000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk4";
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};
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smbclk: oscclk5 {
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/* SMB clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 5>;
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freq-range = <25000000 60000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk5";
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};
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temp-dcc {
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/* DCC internal operating temperature */
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compatible = "arm,vexpress-temp";
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arm,vexpress-sysreg,func = <4 0>;
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label = "DCC";
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};
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};
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smb: smb@8000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x08000000 0x04000000>,
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<1 0 0x14000000 0x04000000>,
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<2 0 0x18000000 0x04000000>,
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<3 0 0x1c000000 0x04000000>,
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<4 0 0x0c000000 0x04000000>,
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<5 0 0x10000000 0x04000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 63>;
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interrupt-map = <0 0 0 &gic 0 0 4>,
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<0 0 1 &gic 0 1 4>,
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<0 0 2 &gic 0 2 4>,
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<0 0 3 &gic 0 3 4>,
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<0 0 4 &gic 0 4 4>,
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<0 0 5 &gic 0 5 4>,
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<0 0 6 &gic 0 6 4>,
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<0 0 7 &gic 0 7 4>,
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<0 0 8 &gic 0 8 4>,
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<0 0 9 &gic 0 9 4>,
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<0 0 10 &gic 0 10 4>,
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<0 0 11 &gic 0 11 4>,
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<0 0 12 &gic 0 12 4>,
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<0 0 13 &gic 0 13 4>,
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<0 0 14 &gic 0 14 4>,
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<0 0 15 &gic 0 15 4>,
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<0 0 16 &gic 0 16 4>,
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<0 0 17 &gic 0 17 4>,
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<0 0 18 &gic 0 18 4>,
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<0 0 19 &gic 0 19 4>,
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<0 0 20 &gic 0 20 4>,
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<0 0 21 &gic 0 21 4>,
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<0 0 22 &gic 0 22 4>,
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<0 0 23 &gic 0 23 4>,
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<0 0 24 &gic 0 24 4>,
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<0 0 25 &gic 0 25 4>,
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<0 0 26 &gic 0 26 4>,
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<0 0 27 &gic 0 27 4>,
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<0 0 28 &gic 0 28 4>,
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<0 0 29 &gic 0 29 4>,
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<0 0 30 &gic 0 30 4>,
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<0 0 31 &gic 0 31 4>,
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<0 0 32 &gic 0 32 4>,
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<0 0 33 &gic 0 33 4>,
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<0 0 34 &gic 0 34 4>,
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<0 0 35 &gic 0 35 4>,
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<0 0 36 &gic 0 36 4>,
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<0 0 37 &gic 0 37 4>,
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<0 0 38 &gic 0 38 4>,
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<0 0 39 &gic 0 39 4>,
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<0 0 40 &gic 0 40 4>,
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<0 0 41 &gic 0 41 4>,
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<0 0 42 &gic 0 42 4>;
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};
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site2: hsb@40000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x40000000 0x40000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 3>;
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interrupt-map = <0 0 &gic 0 36 4>,
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<0 1 &gic 0 37 4>,
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<0 2 &gic 0 38 4>,
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<0 3 &gic 0 39 4>;
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};
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};
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