mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 07:26:46 +07:00
00f7ed8d89
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
565 lines
13 KiB
Plaintext
565 lines
13 KiB
Plaintext
/*
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* Copyright 2013 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/include/ "skeleton.dtsi"
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/ {
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interrupt-parent = <&gic>;
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aliases {
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ethernet0 = &emac;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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};
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cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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};
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};
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memory {
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reg = <0x40000000 0x80000000>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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osc24M: osc24M@01c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-osc-clk";
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reg = <0x01c20050 0x4>;
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clock-frequency = <24000000>;
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};
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osc32k: osc32k {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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pll1: pll1@01c20000 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-pll1-clk";
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reg = <0x01c20000 0x4>;
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clocks = <&osc24M>;
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};
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pll4: pll4@01c20018 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-pll1-clk";
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reg = <0x01c20018 0x4>;
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clocks = <&osc24M>;
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};
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pll5: pll5@01c20020 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-pll5-clk";
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reg = <0x01c20020 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll5_ddr", "pll5_other";
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};
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pll6: pll6@01c20028 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-pll6-clk";
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reg = <0x01c20028 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll6_sata", "pll6_other", "pll6";
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};
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-cpu-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
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};
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axi: axi@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-axi-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&cpu>;
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};
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ahb: ahb@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-ahb-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&axi>;
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};
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ahb_gates: ahb_gates@01c20060 {
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#clock-cells = <1>;
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compatible = "allwinner,sun7i-a20-ahb-gates-clk";
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reg = <0x01c20060 0x8>;
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clocks = <&ahb>;
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clock-output-names = "ahb_usb0", "ahb_ehci0",
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"ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
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"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
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"ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
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"ahb_nand", "ahb_sdram", "ahb_ace",
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"ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
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"ahb_spi2", "ahb_spi3", "ahb_sata",
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"ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
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"ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
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"ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
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"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
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"ahb_de_fe1", "ahb_gmac", "ahb_mp",
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"ahb_mali";
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};
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apb0: apb0@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-apb0-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&ahb>;
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};
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apb0_gates: apb0_gates@01c20068 {
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#clock-cells = <1>;
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compatible = "allwinner,sun7i-a20-apb0-gates-clk";
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reg = <0x01c20068 0x4>;
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clocks = <&apb0>;
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clock-output-names = "apb0_codec", "apb0_spdif",
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"apb0_ac97", "apb0_iis0", "apb0_iis1",
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"apb0_pio", "apb0_ir0", "apb0_ir1",
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"apb0_iis2", "apb0_keypad";
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};
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apb1_mux: apb1_mux@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-apb1-mux-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
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};
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apb1: apb1@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-apb1-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&apb1_mux>;
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};
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apb1_gates: apb1_gates@01c2006c {
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#clock-cells = <1>;
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compatible = "allwinner,sun7i-a20-apb1-gates-clk";
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reg = <0x01c2006c 0x4>;
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clocks = <&apb1>;
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clock-output-names = "apb1_i2c0", "apb1_i2c1",
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"apb1_i2c2", "apb1_i2c3", "apb1_can",
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"apb1_scr", "apb1_ps20", "apb1_ps21",
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"apb1_i2c4", "apb1_uart0", "apb1_uart1",
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"apb1_uart2", "apb1_uart3", "apb1_uart4",
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"apb1_uart5", "apb1_uart6", "apb1_uart7";
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};
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nand_clk: clk@01c20080 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c20080 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "nand";
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};
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ms_clk: clk@01c20084 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c20084 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ms";
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};
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mmc0_clk: clk@01c20088 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c20088 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc0";
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};
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mmc1_clk: clk@01c2008c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c2008c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc1";
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};
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mmc2_clk: clk@01c20090 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c20090 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc2";
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};
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mmc3_clk: clk@01c20094 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c20094 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc3";
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};
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ts_clk: clk@01c20098 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c20098 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ts";
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};
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ss_clk: clk@01c2009c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c2009c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ss";
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};
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spi0_clk: clk@01c200a0 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c200a0 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "spi0";
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};
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spi1_clk: clk@01c200a4 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c200a4 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "spi1";
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};
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spi2_clk: clk@01c200a8 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c200a8 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "spi2";
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};
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pata_clk: clk@01c200ac {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c200ac 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "pata";
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};
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ir0_clk: clk@01c200b0 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c200b0 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ir0";
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};
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ir1_clk: clk@01c200b4 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c200b4 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ir1";
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};
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spi3_clk: clk@01c200d4 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c200d4 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "spi3";
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};
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mbus_clk: clk@01c2015c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c2015c 0x4>;
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clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
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clock-output-names = "mbus";
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};
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};
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soc@01c00000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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emac: ethernet@01c0b000 {
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compatible = "allwinner,sun4i-emac";
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reg = <0x01c0b000 0x1000>;
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interrupts = <0 55 1>;
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clocks = <&ahb_gates 17>;
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status = "disabled";
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};
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mdio@01c0b080 {
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compatible = "allwinner,sun4i-mdio";
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reg = <0x01c0b080 0x14>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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pio: pinctrl@01c20800 {
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compatible = "allwinner,sun7i-a20-pinctrl";
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reg = <0x01c20800 0x400>;
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interrupts = <0 28 1>;
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clocks = <&apb0_gates 5>;
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gpio-controller;
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interrupt-controller;
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#address-cells = <1>;
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#size-cells = <0>;
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#gpio-cells = <3>;
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uart0_pins_a: uart0@0 {
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allwinner,pins = "PB22", "PB23";
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allwinner,function = "uart0";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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uart6_pins_a: uart6@0 {
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allwinner,pins = "PI12", "PI13";
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allwinner,function = "uart6";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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uart7_pins_a: uart7@0 {
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allwinner,pins = "PI20", "PI21";
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allwinner,function = "uart7";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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i2c0_pins_a: i2c0@0 {
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allwinner,pins = "PB0", "PB1";
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allwinner,function = "i2c0";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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i2c1_pins_a: i2c1@0 {
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allwinner,pins = "PB18", "PB19";
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allwinner,function = "i2c1";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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i2c2_pins_a: i2c2@0 {
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allwinner,pins = "PB20", "PB21";
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allwinner,function = "i2c2";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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emac_pins_a: emac0@0 {
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allwinner,pins = "PA0", "PA1", "PA2",
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"PA3", "PA4", "PA5", "PA6",
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"PA7", "PA8", "PA9", "PA10",
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"PA11", "PA12", "PA13", "PA14",
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"PA15", "PA16";
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allwinner,function = "emac";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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};
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timer@01c20c00 {
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compatible = "allwinner,sun4i-timer";
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reg = <0x01c20c00 0x90>;
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interrupts = <0 22 1>,
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<0 23 1>,
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<0 24 1>,
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<0 25 1>,
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<0 67 1>,
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<0 68 1>;
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clocks = <&osc24M>;
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};
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wdt: watchdog@01c20c90 {
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compatible = "allwinner,sun4i-wdt";
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reg = <0x01c20c90 0x10>;
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};
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rtc: rtc@01c20d00 {
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compatible = "allwinner,sun7i-a20-rtc";
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reg = <0x01c20d00 0x20>;
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interrupts = <0 24 1>;
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};
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sid: eeprom@01c23800 {
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compatible = "allwinner,sun7i-a20-sid";
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reg = <0x01c23800 0x200>;
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};
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rtp: rtp@01c25000 {
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compatible = "allwinner,sun4i-ts";
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reg = <0x01c25000 0x100>;
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interrupts = <0 29 4>;
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};
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uart0: serial@01c28000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28000 0x400>;
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interrupts = <0 1 1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb1_gates 16>;
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status = "disabled";
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};
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uart1: serial@01c28400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28400 0x400>;
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interrupts = <0 2 1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb1_gates 17>;
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status = "disabled";
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};
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uart2: serial@01c28800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28800 0x400>;
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interrupts = <0 3 1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb1_gates 18>;
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status = "disabled";
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};
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uart3: serial@01c28c00 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28c00 0x400>;
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interrupts = <0 4 1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb1_gates 19>;
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status = "disabled";
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};
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uart4: serial@01c29000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c29000 0x400>;
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interrupts = <0 17 1>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb1_gates 20>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@01c29400 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29400 0x400>;
|
|
interrupts = <0 18 1>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb1_gates 21>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart6: serial@01c29800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29800 0x400>;
|
|
interrupts = <0 19 1>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb1_gates 22>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart7: serial@01c29c00 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29c00 0x400>;
|
|
interrupts = <0 20 1>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb1_gates 23>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@01c2ac00 {
|
|
compatible = "allwinner,sun4i-i2c";
|
|
reg = <0x01c2ac00 0x400>;
|
|
interrupts = <0 7 1>;
|
|
clocks = <&apb1_gates 0>;
|
|
clock-frequency = <100000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@01c2b000 {
|
|
compatible = "allwinner,sun4i-i2c";
|
|
reg = <0x01c2b000 0x400>;
|
|
interrupts = <0 8 1>;
|
|
clocks = <&apb1_gates 1>;
|
|
clock-frequency = <100000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@01c2b400 {
|
|
compatible = "allwinner,sun4i-i2c";
|
|
reg = <0x01c2b400 0x400>;
|
|
interrupts = <0 9 1>;
|
|
clocks = <&apb1_gates 2>;
|
|
clock-frequency = <100000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@01c2b800 {
|
|
compatible = "allwinner,sun4i-i2c";
|
|
reg = <0x01c2b800 0x400>;
|
|
interrupts = <0 88 1>;
|
|
clocks = <&apb1_gates 3>;
|
|
clock-frequency = <100000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@01c2bc00 {
|
|
compatible = "allwinner,sun4i-i2c";
|
|
reg = <0x01c2bc00 0x400>;
|
|
interrupts = <0 89 1>;
|
|
clocks = <&apb1_gates 15>;
|
|
clock-frequency = <100000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gic: interrupt-controller@01c81000 {
|
|
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
|
|
reg = <0x01c81000 0x1000>,
|
|
<0x01c82000 0x1000>,
|
|
<0x01c84000 0x2000>,
|
|
<0x01c86000 0x2000>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupts = <1 9 0xf04>;
|
|
};
|
|
};
|
|
};
|