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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 01:36:47 +07:00
daa1c164db
cx18: cx18_writel_expect() should not declare success on a PCI read error. This removes the potential for cx18_write*_expect() calls to not accomplish a PCI write successfully as expected. The CX18-AV core uses the *expect() calls often and this may be the source of intermittent audio problems and standands switching problems. Signed-off-by: Andy Walls <awalls@radix.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
192 lines
4.8 KiB
C
192 lines
4.8 KiB
C
/*
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* cx18 driver PCI memory mapped IO access routines
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*
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* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
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* Copyright (C) 2008 Andy Walls <awalls@radix.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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* 02111-1307 USA
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*/
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#ifndef CX18_IO_H
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#define CX18_IO_H
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#include "cx18-driver.h"
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/*
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* Readback and retry of MMIO access for reliability:
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* The concept was suggested by Steve Toth <stoth@linuxtv.org>.
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* The implmentation is the fault of Andy Walls <awalls@radix.net>.
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*
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* *write* functions are implied to retry the mmio unless suffixed with _noretry
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* *read* functions never retry the mmio (it never helps to do so)
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*/
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/* Non byteswapping memory mapped IO */
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static inline u32 cx18_raw_readl(struct cx18 *cx, const void __iomem *addr)
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{
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return __raw_readl(addr);
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}
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static inline
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void cx18_raw_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr)
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{
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__raw_writel(val, addr);
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}
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static inline void cx18_raw_writel(struct cx18 *cx, u32 val, void __iomem *addr)
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{
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int i;
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for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
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cx18_raw_writel_noretry(cx, val, addr);
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if (val == cx18_raw_readl(cx, addr))
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break;
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}
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}
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/* Normal memory mapped IO */
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static inline u32 cx18_readl(struct cx18 *cx, const void __iomem *addr)
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{
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return readl(addr);
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}
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static inline
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void cx18_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr)
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{
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writel(val, addr);
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}
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static inline void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr)
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{
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int i;
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for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
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cx18_writel_noretry(cx, val, addr);
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if (val == cx18_readl(cx, addr))
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break;
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}
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}
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static inline
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void cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr,
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u32 eval, u32 mask)
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{
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int i;
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u32 r;
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eval &= mask;
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for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
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cx18_writel_noretry(cx, val, addr);
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r = cx18_readl(cx, addr);
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if (r == 0xffffffff && eval != 0xffffffff)
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continue;
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if (eval == (r & mask))
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break;
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}
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}
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static inline u16 cx18_readw(struct cx18 *cx, const void __iomem *addr)
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{
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return readw(addr);
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}
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static inline
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void cx18_writew_noretry(struct cx18 *cx, u16 val, void __iomem *addr)
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{
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writew(val, addr);
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}
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static inline void cx18_writew(struct cx18 *cx, u16 val, void __iomem *addr)
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{
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int i;
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for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
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cx18_writew_noretry(cx, val, addr);
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if (val == cx18_readw(cx, addr))
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break;
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}
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}
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static inline u8 cx18_readb(struct cx18 *cx, const void __iomem *addr)
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{
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return readb(addr);
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}
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static inline
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void cx18_writeb_noretry(struct cx18 *cx, u8 val, void __iomem *addr)
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{
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writeb(val, addr);
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}
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static inline void cx18_writeb(struct cx18 *cx, u8 val, void __iomem *addr)
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{
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int i;
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for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
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cx18_writeb_noretry(cx, val, addr);
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if (val == cx18_readb(cx, addr))
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break;
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}
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}
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static inline
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void cx18_memcpy_fromio(struct cx18 *cx, void *to,
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const void __iomem *from, unsigned int len)
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{
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memcpy_fromio(to, from, len);
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}
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void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count);
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/* Access "register" region of CX23418 memory mapped I/O */
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static inline void cx18_write_reg_noretry(struct cx18 *cx, u32 val, u32 reg)
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{
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cx18_writel_noretry(cx, val, cx->reg_mem + reg);
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}
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static inline void cx18_write_reg(struct cx18 *cx, u32 val, u32 reg)
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{
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cx18_writel(cx, val, cx->reg_mem + reg);
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}
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static inline void cx18_write_reg_expect(struct cx18 *cx, u32 val, u32 reg,
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u32 eval, u32 mask)
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{
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cx18_writel_expect(cx, val, cx->reg_mem + reg, eval, mask);
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}
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static inline u32 cx18_read_reg(struct cx18 *cx, u32 reg)
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{
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return cx18_readl(cx, cx->reg_mem + reg);
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}
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/* Access "encoder memory" region of CX23418 memory mapped I/O */
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static inline void cx18_write_enc(struct cx18 *cx, u32 val, u32 addr)
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{
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cx18_writel(cx, val, cx->enc_mem + addr);
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}
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static inline u32 cx18_read_enc(struct cx18 *cx, u32 addr)
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{
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return cx18_readl(cx, cx->enc_mem + addr);
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}
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void cx18_sw1_irq_enable(struct cx18 *cx, u32 val);
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void cx18_sw1_irq_disable(struct cx18 *cx, u32 val);
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void cx18_sw2_irq_enable(struct cx18 *cx, u32 val);
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void cx18_sw2_irq_disable(struct cx18 *cx, u32 val);
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void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val);
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void cx18_setup_page(struct cx18 *cx, u32 addr);
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#endif /* CX18_IO_H */
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