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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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2f4bc73445
The A80 SoC has reset controls matching bus clock gates. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
53 lines
1.1 KiB
Plaintext
53 lines
1.1 KiB
Plaintext
menuconfig ARCH_SUNXI
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bool "Allwinner SoCs" if ARCH_MULTI_V7
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select ARCH_REQUIRE_GPIOLIB
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select CLKSRC_MMIO
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select GENERIC_IRQ_CHIP
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select PINCTRL
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select SUN4I_TIMER
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if ARCH_SUNXI
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config MACH_SUN4I
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bool "Allwinner A10 (sun4i) SoCs support"
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default ARCH_SUNXI
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config MACH_SUN5I
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bool "Allwinner A10s / A13 (sun5i) SoCs support"
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default ARCH_SUNXI
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select SUN5I_HSTIMER
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config MACH_SUN6I
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bool "Allwinner A31 (sun6i) SoCs support"
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default ARCH_SUNXI
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select ARCH_HAS_RESET_CONTROLLER
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select ARM_GIC
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select MFD_SUN6I_PRCM
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select RESET_CONTROLLER
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select SUN5I_HSTIMER
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config MACH_SUN7I
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bool "Allwinner A20 (sun7i) SoCs support"
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default ARCH_SUNXI
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select ARM_GIC
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select ARM_PSCI
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select HAVE_ARM_ARCH_TIMER
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select SUN5I_HSTIMER
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config MACH_SUN8I
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bool "Allwinner A23 (sun8i) SoCs support"
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default ARCH_SUNXI
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select ARCH_HAS_RESET_CONTROLLER
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select ARM_GIC
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select MFD_SUN6I_PRCM
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select RESET_CONTROLLER
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config MACH_SUN9I
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bool "Allwinner (sun9i) SoCs support"
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default ARCH_SUNXI
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select ARCH_HAS_RESET_CONTROLLER
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select ARM_GIC
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select RESET_CONTROLLER
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endif
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