Stefan Agner 22039d150f clk: imx7d: create clocks behind rawnand clock gate ... The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT and NAND_CLK_ROOT. However, the gate has been in the chain of the latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT only, e.g. as required by APBH-Bridge-DMA. Add new clocks which represent the clock after the gate, and use a shared clock gate to correctly model the hardware. Signed-off-by: Stefan Agner <stefan@agner.ch> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Han Xu <han.xu@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>		2017-06-19 19:02:41 -07:00
..
clk-busy.c
clk-cpu.c
clk-fixup-div.c
clk-fixup-mux.c
clk-gate2.c
clk-gate-exclusive.c
clk-imx1.c
clk-imx6q.c	clk: imx6: don't restrict LDB mux changes on QuadPlus	2017-01-20 15:22:37 -08:00
clk-imx6sl.c
clk-imx6sx.c
clk-imx6ul.c	clk: imx: correct uart4_serial clock name in driver for i.MX6UL	2017-04-12 18:51:36 +02:00
clk-imx7d.c	clk: imx7d: create clocks behind rawnand clock gate	2017-06-19 19:02:41 -07:00
clk-imx21.c
clk-imx25.c
clk-imx27.c
clk-imx31.c	ARM: clk: imx31: properly init clocks for machines with DT	2016-11-01 16:44:46 +08:00
clk-imx35.c
clk-imx51-imx53.c
clk-pfd.c
clk-pllv1.c
clk-pllv2.c
clk-pllv3.c	clk: imx7d: Fix the DDR PLL enable bit	2017-06-06 17:42:41 -07:00
clk-vf610.c	clk: imx: pllv3: support fractional multiplier on vf610 PLL1/PLL2	2017-01-09 16:06:41 -08:00
clk.c
clk.h	clk: imx7d: Fix the powerdown bit location of PLL DDR	2017-06-01 00:25:38 -07:00
Makefile