Zhan Liu 00d22e9e04 drm/amd/display: Add missing HBM support and raise Vega20's uclk. ... [Why] When more than 2 displays are connected to the graphics card, only the minimum memory clock is needed. However, when more displays are connected, the minimum memory clock is not sufficient enough to support the overwhelming bandwidth. System will hang under this circumstance. Also, the old code didn't address HBM cards, which has 2 pseudo channels. We need to add the HBM part here. [How] When graphics card connects to 2 or more displays, switch to high memory clock. Also, choose memory multiplier based on whether its regular DRAM or HBM. Signed-off-by: Zhan Liu <zhan.liu@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-10-03 09:10:57 -05:00
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acp
amdgpu	drm/amdgpu: cleanup creating BOs at fixed location (v2)	2019-09-17 08:06:54 -05:00
amdkfd	drm/amdkfd: Swap trap temporary registers in gfx10 trap handler	2019-09-16 15:28:31 -05:00
display	drm/amd/display: Add missing HBM support and raise Vega20's uclk.	2019-10-03 09:10:57 -05:00
include	drm/amdgpu: add pcie bif ras related registers	2019-09-16 10:09:37 -05:00
powerplay	drm/amd/amdgpu: power up sdma engine when S3 resume back	2019-09-16 10:16:07 -05:00