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2374a5399b
The HSI2C module on Exynos7 differs in the transfer status bits. Transfer status bits were moved to INT_ENABLE and INT_STATUS registers This patch adds support for the HSI2C module on Exynos7. 1. Implementes a "hw" field in the variant struct to distinguish the hardware. 2. Updates the dt-new compatible in dt-binding documenation Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
54 lines
1.6 KiB
Plaintext
54 lines
1.6 KiB
Plaintext
* Samsung's High Speed I2C controller
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The Samsung's High Speed I2C controller is used to interface with I2C devices
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at various speeds ranging from 100khz to 3.4Mhz.
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Required properties:
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- compatible: value should be.
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-> "samsung,exynos5-hsi2c", (DEPRECATED)
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for i2c compatible with HSI2C available
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on Exynos5250 and Exynos5420 SoCs.
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-> "samsung,exynos5250-hsi2c", for i2c compatible with HSI2C available
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on Exynos5250 and Exynos5420 SoCs.
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-> "samsung,exynos5260-hsi2c", for i2c compatible with HSI2C available
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on Exynos5260 SoCs.
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-> "samsung,exynos7-hsi2c", for i2c compatible with HSI2C available
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on Exynos7 SoCs.
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- reg: physical base address of the controller and length of memory mapped
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region.
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- interrupts: interrupt number to the cpu.
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- #address-cells: always 1 (for i2c addresses)
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- #size-cells: always 0
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- Pinctrl:
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- pinctrl-0: Pin control group to be used for this controller.
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- pinctrl-names: Should contain only one value - "default".
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Optional properties:
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- clock-frequency: Desired operating frequency in Hz of the bus.
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-> If not specified, the bus operates in fast-speed mode at
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at 100khz.
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-> If specified, the bus operates in high-speed mode only if the
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clock-frequency is >= 1Mhz.
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Example:
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hsi2c@12ca0000 {
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compatible = "samsung,exynos5250-hsi2c";
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reg = <0x12ca0000 0x100>;
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interrupts = <56>;
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clock-frequency = <100000>;
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pinctrl-0 = <&i2c4_bus>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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s2mps11_pmic@66 {
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compatible = "samsung,s2mps11-pmic";
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reg = <0x66>;
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};
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};
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