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4831e0d905
Starting from Tangier B0 and continuing on Anniedale the HSU DMA interrupt line is actually shared with UART. Handling them independently is racy and quite often comes with the following traceback. irq 54: nobody cared (try booting with the "irqpoll" option) CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.9.0-rc6-edison64-86244934+ #1 Hardware name: Intel Corporation Merrifield/BODEGA BAY, BIOS 542 2015.01.21:18.19.48 ffff88003f203eb0 ffffffff8130e718 ffff880032627000 ffff88003262709c ffff88003f203ed8 ffffffff810a3960 ffff880032627000 0000000000000000 ffff880032627000 ffff88003f203f10 ffffffff810a3cc7 ffff880032627000 Call Trace: <IRQ> [<ffffffff8130e718>] dump_stack+0x4d/0x65 [<ffffffff810a3960>] __report_bad_irq+0x30/0xc0 [<ffffffff810a3cc7>] note_interrupt+0x227/0x270 [<ffffffff810a1380>] handle_irq_event_percpu+0x40/0x50 [<ffffffff810a13b7>] handle_irq_event+0x27/0x50 [<ffffffff810a42d5>] handle_fasteoi_irq+0x85/0x150 [<ffffffff8101d7fe>] handle_irq+0x6e/0x120 [<ffffffff8105b8bc>] ? _local_bh_enable+0x1c/0x50 [<ffffffff8101d0d6>] do_IRQ+0x46/0xd0 [<ffffffff818cef3f>] common_interrupt+0x7f/0x7f <EOI> [<ffffffff818cdead>] ? mwait_idle+0x7d/0x140 [<ffffffff81024c9a>] arch_cpu_idle+0xa/0x10 [<ffffffff818ce150>] default_idle_call+0x20/0x30 [<ffffffff810908fd>] cpu_startup_entry+0x16d/0x1d0 [<ffffffff818c882d>] rest_init+0x6d/0x70 [<ffffffff81f93e8f>] start_kernel+0x3e2/0x3ef [<ffffffff81f9343d>] x86_64_start_reservations+0x38/0x3a [<ffffffff81f93529>] x86_64_start_kernel+0xea/0xed handlers: [<ffffffff81411670>] serial8250_interrupt Disabling IRQ #54 Fix this by handling interrupt only in one place. The issue is discussed here: https://github.com/andy-shev/linux/issues/5 Moreover this also fixes another bug when Rx DMA returns wrong residue and we can't rely on it. Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
147 lines
3.4 KiB
C
147 lines
3.4 KiB
C
/*
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* PCI driver for the High Speed UART DMA
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*
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* Copyright (C) 2015 Intel Corporation
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* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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*
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* Partially based on the bits found in drivers/tty/serial/mfd.c.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include "hsu.h"
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#define HSU_PCI_DMASR 0x00
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#define HSU_PCI_DMAISR 0x04
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#define HSU_PCI_CHAN_OFFSET 0x100
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#define PCI_DEVICE_ID_INTEL_MFLD_HSU_DMA 0x081e
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#define PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA 0x1192
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static irqreturn_t hsu_pci_irq(int irq, void *dev)
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{
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struct hsu_dma_chip *chip = dev;
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struct pci_dev *pdev = to_pci_dev(chip->dev);
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u32 dmaisr;
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u32 status;
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unsigned short i;
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int ret = 0;
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int err;
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/*
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* On Intel Tangier B0 and Anniedale the interrupt line, disregarding
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* to have different numbers, is shared between HSU DMA and UART IPs.
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* Thus on such SoCs we are expecting that IRQ handler is called in
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* UART driver only.
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*/
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if (pdev->device == PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA)
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return IRQ_HANDLED;
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dmaisr = readl(chip->regs + HSU_PCI_DMAISR);
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for (i = 0; i < chip->hsu->nr_channels; i++) {
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if (dmaisr & 0x1) {
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err = hsu_dma_get_status(chip, i, &status);
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if (err > 0)
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ret |= 1;
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else if (err == 0)
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ret |= hsu_dma_do_irq(chip, i, status);
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}
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dmaisr >>= 1;
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}
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return IRQ_RETVAL(ret);
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}
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static int hsu_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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struct hsu_dma_chip *chip;
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int ret;
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ret = pcim_enable_device(pdev);
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if (ret)
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return ret;
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ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
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if (ret) {
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dev_err(&pdev->dev, "I/O memory remapping failed\n");
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return ret;
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}
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pci_set_master(pdev);
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pci_try_set_mwi(pdev);
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ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
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if (ret)
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return ret;
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ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
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if (ret)
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return ret;
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chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
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if (!chip)
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return -ENOMEM;
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ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
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if (ret < 0)
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return ret;
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chip->dev = &pdev->dev;
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chip->regs = pcim_iomap_table(pdev)[0];
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chip->length = pci_resource_len(pdev, 0);
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chip->offset = HSU_PCI_CHAN_OFFSET;
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chip->irq = pci_irq_vector(pdev, 0);
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ret = hsu_dma_probe(chip);
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if (ret)
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return ret;
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ret = request_irq(chip->irq, hsu_pci_irq, 0, "hsu_dma_pci", chip);
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if (ret)
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goto err_register_irq;
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pci_set_drvdata(pdev, chip);
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return 0;
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err_register_irq:
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hsu_dma_remove(chip);
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return ret;
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}
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static void hsu_pci_remove(struct pci_dev *pdev)
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{
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struct hsu_dma_chip *chip = pci_get_drvdata(pdev);
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free_irq(chip->irq, chip);
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hsu_dma_remove(chip);
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}
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static const struct pci_device_id hsu_pci_id_table[] = {
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MFLD_HSU_DMA), 0 },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA), 0 },
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{ }
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};
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MODULE_DEVICE_TABLE(pci, hsu_pci_id_table);
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static struct pci_driver hsu_pci_driver = {
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.name = "hsu_dma_pci",
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.id_table = hsu_pci_id_table,
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.probe = hsu_pci_probe,
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.remove = hsu_pci_remove,
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};
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module_pci_driver(hsu_pci_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("High Speed UART DMA PCI driver");
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MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
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