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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a6528d0172
cciss: Fix hard reset code. Smart Array controllers newer than the P600 do not honor the PCI power state method of resetting the controllers. Instead, in these cases we can get them to reset via the "doorbell" register. This escaped notice until we began using "performant" mode because the fact that the controllers did not reset did not normally impede subsequent operation, and so things generally appeared to "work". Once the performant mode code was added, if the controller does not reset, it remains in performant mode. The code immediately after the reset presumes the controller is in "simple" mode (which previously, it had remained in simple mode the whole time). If the controller remains in performant mode any code which presumes it is in simple mode will not work. So the reset needs to be fixed. Unfortunately there are some controllers which cannot be reset by either method. (eg. p800). We detect these cases by noticing that the controller seems to remain in performant mode even after a reset has been attempted. In those cases we ignore the controller, as any commands outstanding on it will result in stale completions. To sum up, we try to do a better job of resetting the controller if "reset_devices" is set, and if it doesn't work, we ignore that controller. Signed-off-by: Stephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: Jens Axboe <jaxboe@fusionio.com>
258 lines
6.9 KiB
C
258 lines
6.9 KiB
C
#ifndef CCISS_CMD_H
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#define CCISS_CMD_H
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#include <linux/cciss_defs.h>
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/* DEFINES */
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#define CISS_VERSION "1.00"
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/* general boundary definitions */
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#define MAXSGENTRIES 32
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#define CCISS_SG_CHAIN 0x80000000
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#define MAXREPLYQS 256
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/* Unit Attentions ASC's as defined for the MSA2012sa */
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#define POWER_OR_RESET 0x29
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#define STATE_CHANGED 0x2a
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#define UNIT_ATTENTION_CLEARED 0x2f
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#define LUN_FAILED 0x3e
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#define REPORT_LUNS_CHANGED 0x3f
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/* Unit Attentions ASCQ's as defined for the MSA2012sa */
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/* These ASCQ's defined for ASC = POWER_OR_RESET */
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#define POWER_ON_RESET 0x00
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#define POWER_ON_REBOOT 0x01
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#define SCSI_BUS_RESET 0x02
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#define MSA_TARGET_RESET 0x03
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#define CONTROLLER_FAILOVER 0x04
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#define TRANSCEIVER_SE 0x05
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#define TRANSCEIVER_LVD 0x06
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/* These ASCQ's defined for ASC = STATE_CHANGED */
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#define RESERVATION_PREEMPTED 0x03
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#define ASYM_ACCESS_CHANGED 0x06
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#define LUN_CAPACITY_CHANGED 0x09
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/* config space register offsets */
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#define CFG_VENDORID 0x00
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#define CFG_DEVICEID 0x02
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#define CFG_I2OBAR 0x10
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#define CFG_MEM1BAR 0x14
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/* i2o space register offsets */
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#define I2O_IBDB_SET 0x20
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#define I2O_IBDB_CLEAR 0x70
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#define I2O_INT_STATUS 0x30
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#define I2O_INT_MASK 0x34
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#define I2O_IBPOST_Q 0x40
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#define I2O_OBPOST_Q 0x44
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#define I2O_DMA1_CFG 0x214
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/* Configuration Table */
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#define CFGTBL_ChangeReq 0x00000001l
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#define CFGTBL_AccCmds 0x00000001l
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#define DOORBELL_CTLR_RESET 0x00000004l
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#define CFGTBL_Trans_Simple 0x00000002l
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#define CFGTBL_Trans_Performant 0x00000004l
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#define CFGTBL_BusType_Ultra2 0x00000001l
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#define CFGTBL_BusType_Ultra3 0x00000002l
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#define CFGTBL_BusType_Fibre1G 0x00000100l
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#define CFGTBL_BusType_Fibre2G 0x00000200l
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typedef struct _vals32
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{
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__u32 lower;
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__u32 upper;
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} vals32;
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typedef union _u64bit
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{
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vals32 val32;
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__u64 val;
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} u64bit;
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/* Type defs used in the following structs */
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#define QWORD vals32
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/* STRUCTURES */
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#define CISS_MAX_PHYS_LUN 1024
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/* SCSI-3 Cmmands */
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#pragma pack(1)
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#define CISS_INQUIRY 0x12
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/* Date returned */
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typedef struct _InquiryData_struct
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{
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BYTE data_byte[36];
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} InquiryData_struct;
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#define CISS_REPORT_LOG 0xc2 /* Report Logical LUNs */
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#define CISS_REPORT_PHYS 0xc3 /* Report Physical LUNs */
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/* Data returned */
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typedef struct _ReportLUNdata_struct
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{
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BYTE LUNListLength[4];
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DWORD reserved;
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BYTE LUN[CISS_MAX_LUN][8];
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} ReportLunData_struct;
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#define CCISS_READ_CAPACITY 0x25 /* Read Capacity */
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typedef struct _ReadCapdata_struct
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{
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BYTE total_size[4]; /* Total size in blocks */
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BYTE block_size[4]; /* Size of blocks in bytes */
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} ReadCapdata_struct;
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#define CCISS_READ_CAPACITY_16 0x9e /* Read Capacity 16 */
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/* service action to differentiate a 16 byte read capacity from
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other commands that use the 0x9e SCSI op code */
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#define CCISS_READ_CAPACITY_16_SERVICE_ACT 0x10
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typedef struct _ReadCapdata_struct_16
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{
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BYTE total_size[8]; /* Total size in blocks */
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BYTE block_size[4]; /* Size of blocks in bytes */
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BYTE prot_en:1; /* protection enable bit */
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BYTE rto_en:1; /* reference tag own enable bit */
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BYTE reserved:6; /* reserved bits */
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BYTE reserved2[18]; /* reserved bytes per spec */
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} ReadCapdata_struct_16;
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/* Define the supported read/write commands for cciss based controllers */
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#define CCISS_READ_10 0x28 /* Read(10) */
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#define CCISS_WRITE_10 0x2a /* Write(10) */
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#define CCISS_READ_16 0x88 /* Read(16) */
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#define CCISS_WRITE_16 0x8a /* Write(16) */
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/* Define the CDB lengths supported by cciss based controllers */
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#define CDB_LEN10 10
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#define CDB_LEN16 16
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/* BMIC commands */
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#define BMIC_READ 0x26
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#define BMIC_WRITE 0x27
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#define BMIC_CACHE_FLUSH 0xc2
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#define CCISS_CACHE_FLUSH 0x01 /* C2 was already being used by CCISS */
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/* Command List Structure */
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#define CTLR_LUNID "\0\0\0\0\0\0\0\0"
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typedef struct _CommandListHeader_struct {
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BYTE ReplyQueue;
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BYTE SGList;
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HWORD SGTotal;
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QWORD Tag;
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LUNAddr_struct LUN;
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} CommandListHeader_struct;
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typedef struct _ErrDescriptor_struct {
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QWORD Addr;
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DWORD Len;
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} ErrDescriptor_struct;
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typedef struct _SGDescriptor_struct {
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QWORD Addr;
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DWORD Len;
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DWORD Ext;
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} SGDescriptor_struct;
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/* Command types */
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#define CMD_RWREQ 0x00
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#define CMD_IOCTL_PEND 0x01
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#define CMD_SCSI 0x03
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#define CMD_MSG_DONE 0x04
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#define CMD_MSG_TIMEOUT 0x05
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#define CMD_MSG_STALE 0xff
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/* This structure needs to be divisible by COMMANDLIST_ALIGNMENT
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* because low bits of the address are used to to indicate that
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* whether the tag contains an index or an address. PAD_32 and
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* PAD_64 can be adjusted independently as needed for 32-bit
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* and 64-bits systems.
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*/
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#define COMMANDLIST_ALIGNMENT (32)
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#define IS_64_BIT ((sizeof(long) - 4)/4)
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#define IS_32_BIT (!IS_64_BIT)
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#define PAD_32 (0)
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#define PAD_64 (4)
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#define PADSIZE (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64)
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#define DIRECT_LOOKUP_BIT 0x10
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#define DIRECT_LOOKUP_SHIFT 5
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typedef struct _CommandList_struct {
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CommandListHeader_struct Header;
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RequestBlock_struct Request;
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ErrDescriptor_struct ErrDesc;
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SGDescriptor_struct SG[MAXSGENTRIES];
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/* information associated with the command */
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__u32 busaddr; /* physical address of this record */
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ErrorInfo_struct * err_info; /* pointer to the allocated mem */
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int ctlr;
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int cmd_type;
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long cmdindex;
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struct hlist_node list;
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struct request * rq;
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struct completion *waiting;
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int retry_count;
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void * scsi_cmd;
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char pad[PADSIZE];
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} CommandList_struct;
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/* Configuration Table Structure */
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typedef struct _HostWrite_struct {
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DWORD TransportRequest;
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DWORD Reserved;
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DWORD CoalIntDelay;
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DWORD CoalIntCount;
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} HostWrite_struct;
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typedef struct _CfgTable_struct {
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BYTE Signature[4];
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DWORD SpecValence;
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#define SIMPLE_MODE 0x02
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#define PERFORMANT_MODE 0x04
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#define MEMQ_MODE 0x08
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DWORD TransportSupport;
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DWORD TransportActive;
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HostWrite_struct HostWrite;
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DWORD CmdsOutMax;
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DWORD BusTypes;
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DWORD TransMethodOffset;
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BYTE ServerName[16];
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DWORD HeartBeat;
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DWORD SCSI_Prefetch;
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DWORD MaxSGElements;
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DWORD MaxLogicalUnits;
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DWORD MaxPhysicalDrives;
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DWORD MaxPhysicalDrivesPerLogicalUnit;
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DWORD MaxPerformantModeCommands;
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u8 reserved[0x78 - 0x58];
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u32 misc_fw_support; /* offset 0x78 */
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#define MISC_FW_DOORBELL_RESET (0x02)
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} CfgTable_struct;
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struct TransTable_struct {
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u32 BlockFetch0;
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u32 BlockFetch1;
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u32 BlockFetch2;
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u32 BlockFetch3;
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u32 BlockFetch4;
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u32 BlockFetch5;
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u32 BlockFetch6;
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u32 BlockFetch7;
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u32 RepQSize;
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u32 RepQCount;
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u32 RepQCtrAddrLow32;
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u32 RepQCtrAddrHigh32;
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u32 RepQAddr0Low32;
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u32 RepQAddr0High32;
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};
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#pragma pack()
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#endif /* CCISS_CMD_H */
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