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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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dfc657b133
This chip has a control register and can prevent altering saved clock. Without this patch we could have: (arm)root@pac14:~# date Tue May 21 03:08:27 MSK 2013 (arm)root@pac14:~# /etc/init.d/hwclock.sh show Tue May 21 11:13:58 2013 -0.067322 seconds (arm)root@pac14:~# /etc/init.d/hwclock.sh stop [info] Saving the system clock. [info] Hardware Clock updated to Tue May 21 03:09:01 MSK 2013. (arm)root@pac14:~# /etc/init.d/hwclock.sh show Tue May 21 11:14:15 2013 -0.624272 seconds The patch enables write access to rtc before the driver tries to write time and re-disables when time data is written. Signed-off-by: Sergey Yanovich <ynvich@gmail.com> Acked-by: Marc Zyngier <maz@misterjones.org> Cc: Alessandro Zummo <a.zummo@towertech.it> Cc: Sachin Kamat <sachin.kamat@linaro.org> Cc: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
257 lines
6.0 KiB
C
257 lines
6.0 KiB
C
/*
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* Dallas DS1302 RTC Support
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*
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* Copyright (C) 2002 David McCullough
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* Copyright (C) 2003 - 2007 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License version 2. See the file "COPYING" in the main directory of
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* this archive for more details.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/rtc.h>
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#include <linux/io.h>
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#include <linux/bcd.h>
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#define DRV_NAME "rtc-ds1302"
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#define DRV_VERSION "0.1.1"
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#define RTC_CMD_READ 0x81 /* Read command */
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#define RTC_CMD_WRITE 0x80 /* Write command */
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#define RTC_CMD_WRITE_ENABLE 0x00 /* Write enable */
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#define RTC_CMD_WRITE_DISABLE 0x80 /* Write disable */
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#define RTC_ADDR_RAM0 0x20 /* Address of RAM0 */
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#define RTC_ADDR_TCR 0x08 /* Address of trickle charge register */
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#define RTC_ADDR_CTRL 0x07 /* Address of control register */
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#define RTC_ADDR_YEAR 0x06 /* Address of year register */
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#define RTC_ADDR_DAY 0x05 /* Address of day of week register */
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#define RTC_ADDR_MON 0x04 /* Address of month register */
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#define RTC_ADDR_DATE 0x03 /* Address of day of month register */
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#define RTC_ADDR_HOUR 0x02 /* Address of hour register */
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#define RTC_ADDR_MIN 0x01 /* Address of minute register */
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#define RTC_ADDR_SEC 0x00 /* Address of second register */
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#ifdef CONFIG_SH_SECUREEDGE5410
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#include <asm/rtc.h>
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#include <mach/secureedge5410.h>
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#define RTC_RESET 0x1000
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#define RTC_IODATA 0x0800
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#define RTC_SCLK 0x0400
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#define set_dp(x) SECUREEDGE_WRITE_IOPORT(x, 0x1c00)
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#define get_dp() SECUREEDGE_READ_IOPORT()
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#define ds1302_set_tx()
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#define ds1302_set_rx()
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static inline int ds1302_hw_init(void)
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{
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return 0;
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}
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static inline void ds1302_reset(void)
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{
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set_dp(get_dp() & ~(RTC_RESET | RTC_IODATA | RTC_SCLK));
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}
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static inline void ds1302_clock(void)
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{
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set_dp(get_dp() | RTC_SCLK); /* clock high */
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set_dp(get_dp() & ~RTC_SCLK); /* clock low */
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}
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static inline void ds1302_start(void)
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{
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set_dp(get_dp() | RTC_RESET);
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}
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static inline void ds1302_stop(void)
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{
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set_dp(get_dp() & ~RTC_RESET);
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}
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static inline void ds1302_txbit(int bit)
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{
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set_dp((get_dp() & ~RTC_IODATA) | (bit ? RTC_IODATA : 0));
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}
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static inline int ds1302_rxbit(void)
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{
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return !!(get_dp() & RTC_IODATA);
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}
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#else
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#error "Add support for your platform"
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#endif
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static void ds1302_sendbits(unsigned int val)
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{
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int i;
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ds1302_set_tx();
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for (i = 8; (i); i--, val >>= 1) {
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ds1302_txbit(val & 0x1);
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ds1302_clock();
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}
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}
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static unsigned int ds1302_recvbits(void)
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{
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unsigned int val;
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int i;
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ds1302_set_rx();
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for (i = 0, val = 0; (i < 8); i++) {
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val |= (ds1302_rxbit() << i);
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ds1302_clock();
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}
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return val;
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}
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static unsigned int ds1302_readbyte(unsigned int addr)
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{
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unsigned int val;
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ds1302_reset();
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ds1302_start();
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ds1302_sendbits(((addr & 0x3f) << 1) | RTC_CMD_READ);
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val = ds1302_recvbits();
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ds1302_stop();
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return val;
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}
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static void ds1302_writebyte(unsigned int addr, unsigned int val)
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{
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ds1302_reset();
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ds1302_start();
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ds1302_sendbits(((addr & 0x3f) << 1) | RTC_CMD_WRITE);
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ds1302_sendbits(val);
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ds1302_stop();
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}
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static int ds1302_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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tm->tm_sec = bcd2bin(ds1302_readbyte(RTC_ADDR_SEC));
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tm->tm_min = bcd2bin(ds1302_readbyte(RTC_ADDR_MIN));
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tm->tm_hour = bcd2bin(ds1302_readbyte(RTC_ADDR_HOUR));
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tm->tm_wday = bcd2bin(ds1302_readbyte(RTC_ADDR_DAY));
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tm->tm_mday = bcd2bin(ds1302_readbyte(RTC_ADDR_DATE));
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tm->tm_mon = bcd2bin(ds1302_readbyte(RTC_ADDR_MON)) - 1;
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tm->tm_year = bcd2bin(ds1302_readbyte(RTC_ADDR_YEAR));
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if (tm->tm_year < 70)
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tm->tm_year += 100;
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dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
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"mday=%d, mon=%d, year=%d, wday=%d\n",
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__func__,
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tm->tm_sec, tm->tm_min, tm->tm_hour,
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tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday);
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return rtc_valid_tm(tm);
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}
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static int ds1302_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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ds1302_writebyte(RTC_ADDR_CTRL, RTC_CMD_WRITE_ENABLE);
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/* Stop RTC */
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ds1302_writebyte(RTC_ADDR_SEC, ds1302_readbyte(RTC_ADDR_SEC) | 0x80);
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ds1302_writebyte(RTC_ADDR_SEC, bin2bcd(tm->tm_sec));
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ds1302_writebyte(RTC_ADDR_MIN, bin2bcd(tm->tm_min));
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ds1302_writebyte(RTC_ADDR_HOUR, bin2bcd(tm->tm_hour));
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ds1302_writebyte(RTC_ADDR_DAY, bin2bcd(tm->tm_wday));
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ds1302_writebyte(RTC_ADDR_DATE, bin2bcd(tm->tm_mday));
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ds1302_writebyte(RTC_ADDR_MON, bin2bcd(tm->tm_mon + 1));
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ds1302_writebyte(RTC_ADDR_YEAR, bin2bcd(tm->tm_year % 100));
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/* Start RTC */
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ds1302_writebyte(RTC_ADDR_SEC, ds1302_readbyte(RTC_ADDR_SEC) & ~0x80);
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ds1302_writebyte(RTC_ADDR_CTRL, RTC_CMD_WRITE_DISABLE);
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return 0;
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}
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static int ds1302_rtc_ioctl(struct device *dev, unsigned int cmd,
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unsigned long arg)
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{
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switch (cmd) {
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#ifdef RTC_SET_CHARGE
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case RTC_SET_CHARGE:
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{
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int tcs_val;
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if (copy_from_user(&tcs_val, (int __user *)arg, sizeof(int)))
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return -EFAULT;
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ds1302_writebyte(RTC_ADDR_TCR, (0xa0 | tcs_val * 0xf));
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return 0;
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}
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#endif
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}
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return -ENOIOCTLCMD;
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}
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static struct rtc_class_ops ds1302_rtc_ops = {
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.read_time = ds1302_rtc_read_time,
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.set_time = ds1302_rtc_set_time,
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.ioctl = ds1302_rtc_ioctl,
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};
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static int __init ds1302_rtc_probe(struct platform_device *pdev)
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{
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struct rtc_device *rtc;
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if (ds1302_hw_init()) {
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dev_err(&pdev->dev, "Failed to init communication channel");
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return -EINVAL;
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}
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/* Reset */
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ds1302_reset();
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/* Write a magic value to the DS1302 RAM, and see if it sticks. */
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ds1302_writebyte(RTC_ADDR_RAM0, 0x42);
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if (ds1302_readbyte(RTC_ADDR_RAM0) != 0x42) {
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dev_err(&pdev->dev, "Failed to probe");
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return -ENODEV;
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}
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rtc = devm_rtc_device_register(&pdev->dev, "ds1302",
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&ds1302_rtc_ops, THIS_MODULE);
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if (IS_ERR(rtc))
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return PTR_ERR(rtc);
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platform_set_drvdata(pdev, rtc);
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return 0;
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}
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static struct platform_driver ds1302_platform_driver = {
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.driver = {
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.name = DRV_NAME,
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.owner = THIS_MODULE,
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},
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};
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module_platform_driver_probe(ds1302_platform_driver, ds1302_rtc_probe);
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MODULE_DESCRIPTION("Dallas DS1302 RTC driver");
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MODULE_VERSION(DRV_VERSION);
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MODULE_AUTHOR("Paul Mundt, David McCullough");
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MODULE_LICENSE("GPL v2");
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