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ef0b27d4cc
According to the standard, the SWITCH command should be followed by a SEND_STATUS command to check for errors. Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com> Acked-by: Matt Fleming <matt@console-pimps.org> Cc: Ian Molton <ian@mnementh.co.uk> Cc: "Roberto A. Foglietta" <roberto.foglietta@gmail.com> Cc: Jarkko Lavinen <jarkko.lavinen@nokia.com> Cc: Denis Karpov <ext-denis.2.karpov@nokia.com> Cc: Pierre Ossman <pierre@ossman.eu> Cc: Philip Langdale <philipl@overt.org> Cc: "Madhusudhan" <madhu.cr@ti.com> Cc: <linux-mmc@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
287 lines
10 KiB
C
287 lines
10 KiB
C
/*
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* Header for MultiMediaCard (MMC)
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*
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* Copyright 2002 Hewlett-Packard Company
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*
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* Use consistent with the GNU GPL is permitted,
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* provided that this copyright notice is
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* preserved in its entirety in all copies and derived works.
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*
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* HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
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* AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
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* FITNESS FOR ANY PARTICULAR PURPOSE.
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*
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* Many thanks to Alessandro Rubini and Jonathan Corbet!
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*
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* Based strongly on code by:
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*
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* Author: Yong-iL Joh <tolkien@mizi.com>
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*
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* Author: Andrew Christian
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* 15 May 2002
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*/
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#ifndef MMC_MMC_H
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#define MMC_MMC_H
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/* Standard MMC commands (4.1) type argument response */
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/* class 1 */
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#define MMC_GO_IDLE_STATE 0 /* bc */
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#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
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#define MMC_ALL_SEND_CID 2 /* bcr R2 */
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#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
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#define MMC_SET_DSR 4 /* bc [31:16] RCA */
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#define MMC_SLEEP_AWAKE 5 /* ac [31:16] RCA 15:flg R1b */
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#define MMC_SWITCH 6 /* ac [31:0] See below R1b */
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#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */
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#define MMC_SEND_EXT_CSD 8 /* adtc R1 */
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#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */
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#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */
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#define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */
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#define MMC_STOP_TRANSMISSION 12 /* ac R1b */
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#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
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#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
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#define MMC_SPI_READ_OCR 58 /* spi spi_R3 */
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#define MMC_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */
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/* class 2 */
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#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
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#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
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#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
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/* class 3 */
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#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
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/* class 4 */
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#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
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#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
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#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
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#define MMC_PROGRAM_CID 26 /* adtc R1 */
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#define MMC_PROGRAM_CSD 27 /* adtc R1 */
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/* class 6 */
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#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
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#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
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#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
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/* class 5 */
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#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
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#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
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#define MMC_ERASE 38 /* ac R1b */
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/* class 9 */
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#define MMC_FAST_IO 39 /* ac <Complex> R4 */
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#define MMC_GO_IRQ_STATE 40 /* bcr R5 */
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/* class 7 */
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#define MMC_LOCK_UNLOCK 42 /* adtc R1b */
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/* class 8 */
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#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
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#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */
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/*
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* MMC_SWITCH argument format:
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*
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* [31:26] Always 0
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* [25:24] Access Mode
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* [23:16] Location of target Byte in EXT_CSD
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* [15:08] Value Byte
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* [07:03] Always 0
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* [02:00] Command Set
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*/
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/*
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MMC status in R1, for native mode (SPI bits are different)
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Type
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e : error bit
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s : status bit
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r : detected and set for the actual command response
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x : detected and set during command execution. the host must poll
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the card by sending status command in order to read these bits.
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Clear condition
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a : according to the card state
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b : always related to the previous command. Reception of
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a valid command will clear it (with a delay of one command)
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c : clear by read
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*/
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#define R1_OUT_OF_RANGE (1 << 31) /* er, c */
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#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
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#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
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#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
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#define R1_ERASE_PARAM (1 << 27) /* ex, c */
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#define R1_WP_VIOLATION (1 << 26) /* erx, c */
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#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
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#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
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#define R1_COM_CRC_ERROR (1 << 23) /* er, b */
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#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
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#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
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#define R1_CC_ERROR (1 << 20) /* erx, c */
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#define R1_ERROR (1 << 19) /* erx, c */
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#define R1_UNDERRUN (1 << 18) /* ex, c */
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#define R1_OVERRUN (1 << 17) /* ex, c */
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#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
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#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
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#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
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#define R1_ERASE_RESET (1 << 13) /* sr, c */
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#define R1_STATUS(x) (x & 0xFFFFE000)
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#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
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#define R1_READY_FOR_DATA (1 << 8) /* sx, a */
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#define R1_SWITCH_ERROR (1 << 7) /* sx, c */
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#define R1_APP_CMD (1 << 5) /* sr, c */
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/*
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* MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS
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* R1 is the low order byte; R2 is the next highest byte, when present.
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*/
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#define R1_SPI_IDLE (1 << 0)
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#define R1_SPI_ERASE_RESET (1 << 1)
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#define R1_SPI_ILLEGAL_COMMAND (1 << 2)
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#define R1_SPI_COM_CRC (1 << 3)
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#define R1_SPI_ERASE_SEQ (1 << 4)
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#define R1_SPI_ADDRESS (1 << 5)
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#define R1_SPI_PARAMETER (1 << 6)
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/* R1 bit 7 is always zero */
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#define R2_SPI_CARD_LOCKED (1 << 8)
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#define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */
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#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
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#define R2_SPI_ERROR (1 << 10)
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#define R2_SPI_CC_ERROR (1 << 11)
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#define R2_SPI_CARD_ECC_ERROR (1 << 12)
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#define R2_SPI_WP_VIOLATION (1 << 13)
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#define R2_SPI_ERASE_PARAM (1 << 14)
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#define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */
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#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE
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/* These are unpacked versions of the actual responses */
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struct _mmc_csd {
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u8 csd_structure;
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u8 spec_vers;
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u8 taac;
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u8 nsac;
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u8 tran_speed;
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u16 ccc;
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u8 read_bl_len;
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u8 read_bl_partial;
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u8 write_blk_misalign;
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u8 read_blk_misalign;
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u8 dsr_imp;
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u16 c_size;
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u8 vdd_r_curr_min;
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u8 vdd_r_curr_max;
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u8 vdd_w_curr_min;
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u8 vdd_w_curr_max;
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u8 c_size_mult;
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union {
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struct { /* MMC system specification version 3.1 */
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u8 erase_grp_size;
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u8 erase_grp_mult;
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} v31;
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struct { /* MMC system specification version 2.2 */
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u8 sector_size;
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u8 erase_grp_size;
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} v22;
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} erase;
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u8 wp_grp_size;
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u8 wp_grp_enable;
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u8 default_ecc;
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u8 r2w_factor;
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u8 write_bl_len;
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u8 write_bl_partial;
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u8 file_format_grp;
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u8 copy;
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u8 perm_write_protect;
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u8 tmp_write_protect;
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u8 file_format;
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u8 ecc;
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};
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/*
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* OCR bits are mostly in host.h
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*/
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#define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */
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/*
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* Card Command Classes (CCC)
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*/
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#define CCC_BASIC (1<<0) /* (0) Basic protocol functions */
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/* (CMD0,1,2,3,4,7,9,10,12,13,15) */
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/* (and for SPI, CMD58,59) */
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#define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */
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/* (CMD11) */
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#define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */
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/* (CMD16,17,18) */
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#define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */
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/* (CMD20) */
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#define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */
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/* (CMD16,24,25,26,27) */
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#define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */
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/* (CMD32,33,34,35,36,37,38,39) */
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#define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */
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/* (CMD28,29,30) */
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#define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */
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/* (CMD16,CMD42) */
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#define CCC_APP_SPEC (1<<8) /* (8) Application specific */
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/* (CMD55,56,57,ACMD*) */
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#define CCC_IO_MODE (1<<9) /* (9) I/O mode */
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/* (CMD5,39,40,52,53) */
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#define CCC_SWITCH (1<<10) /* (10) High speed switch */
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/* (CMD6,34,35,36,37,50) */
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/* (11) Reserved */
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/* (CMD?) */
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/*
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* CSD field definitions
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*/
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#define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */
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#define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */
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#define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1 */
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#define CSD_STRUCT_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */
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#define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */
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#define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */
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#define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */
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#define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 - 3.2 - 3.31 */
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#define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 - 4.1 */
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/*
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* EXT_CSD fields
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*/
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#define EXT_CSD_BUS_WIDTH 183 /* R/W */
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#define EXT_CSD_HS_TIMING 185 /* R/W */
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#define EXT_CSD_CARD_TYPE 196 /* RO */
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#define EXT_CSD_REV 192 /* RO */
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#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
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#define EXT_CSD_S_A_TIMEOUT 217
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/*
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* EXT_CSD field definitions
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*/
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#define EXT_CSD_CMD_SET_NORMAL (1<<0)
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#define EXT_CSD_CMD_SET_SECURE (1<<1)
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#define EXT_CSD_CMD_SET_CPSECURE (1<<2)
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#define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */
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#define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */
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#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
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#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
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#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
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/*
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* MMC_SWITCH access modes
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*/
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#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
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#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */
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#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */
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#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */
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#endif /* MMC_MMC_PROTOCOL_H */
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