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ae150435b5
Moves the SMC (SMSC) drivers into drivers/net/ethernet/smsc/ and the necessary Kconfig and Makefile changes. Also did some cleanup of NET_VENDOR_SMC Kconfig tag for the 8390 based drivers. CC: Nicolas Pitre <nico@fluxnic.net> CC: Donald Becker <becker@scyld.com> CC: Erik Stahlman <erik@vt.edu> CC: Dustin McIntire <dustin@sensoria.com> CC: Steve Glendinning <steve.glendinning@smsc.com> CC: David Hinds <dahinds@users.sourceforge.net> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
242 lines
6.7 KiB
C
242 lines
6.7 KiB
C
/*------------------------------------------------------------------------
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. smc9194.h
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. Copyright (C) 1996 by Erik Stahlman
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.
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. This software may be used and distributed according to the terms
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. of the GNU General Public License, incorporated herein by reference.
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.
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. This file contains register information and access macros for
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. the SMC91xxx chipset.
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.
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. Information contained in this file was obtained from the SMC91C94
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. manual from SMC. To get a copy, if you really want one, you can find
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. information under www.smc.com in the components division.
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. ( this thanks to advice from Donald Becker ).
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.
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. Authors
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. Erik Stahlman ( erik@vt.edu )
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.
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. History
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. 01/06/96 Erik Stahlman moved definitions here from main .c file
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. 01/19/96 Erik Stahlman polished this up some, and added better
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. error handling
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.
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---------------------------------------------------------------------------*/
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#ifndef _SMC9194_H_
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#define _SMC9194_H_
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/* I want some simple types */
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typedef unsigned char byte;
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typedef unsigned short word;
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typedef unsigned long int dword;
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/* Because of bank switching, the SMC91xxx uses only 16 I/O ports */
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#define SMC_IO_EXTENT 16
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/*---------------------------------------------------------------
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.
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. A description of the SMC registers is probably in order here,
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. although for details, the SMC datasheet is invaluable.
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.
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. Basically, the chip has 4 banks of registers ( 0 to 3 ), which
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. are accessed by writing a number into the BANK_SELECT register
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. ( I also use a SMC_SELECT_BANK macro for this ).
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.
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. The banks are configured so that for most purposes, bank 2 is all
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. that is needed for simple run time tasks.
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-----------------------------------------------------------------------*/
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/*
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. Bank Select Register:
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.
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. yyyy yyyy 0000 00xx
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. xx = bank number
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. yyyy yyyy = 0x33, for identification purposes.
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*/
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#define BANK_SELECT 14
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/* BANK 0 */
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#define TCR 0 /* transmit control register */
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#define TCR_ENABLE 0x0001 /* if this is 1, we can transmit */
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#define TCR_FDUPLX 0x0800 /* receive packets sent out */
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#define TCR_STP_SQET 0x1000 /* stop transmitting if Signal quality error */
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#define TCR_MON_CNS 0x0400 /* monitors the carrier status */
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#define TCR_PAD_ENABLE 0x0080 /* pads short packets to 64 bytes */
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#define TCR_CLEAR 0 /* do NOTHING */
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/* the normal settings for the TCR register : */
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/* QUESTION: do I want to enable padding of short packets ? */
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#define TCR_NORMAL TCR_ENABLE
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#define EPH_STATUS 2
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#define ES_LINK_OK 0x4000 /* is the link integrity ok ? */
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#define RCR 4
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#define RCR_SOFTRESET 0x8000 /* resets the chip */
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#define RCR_STRIP_CRC 0x200 /* strips CRC */
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#define RCR_ENABLE 0x100 /* IFF this is set, we can receive packets */
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#define RCR_ALMUL 0x4 /* receive all multicast packets */
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#define RCR_PROMISC 0x2 /* enable promiscuous mode */
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/* the normal settings for the RCR register : */
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#define RCR_NORMAL (RCR_STRIP_CRC | RCR_ENABLE)
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#define RCR_CLEAR 0x0 /* set it to a base state */
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#define COUNTER 6
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#define MIR 8
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#define MCR 10
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/* 12 is reserved */
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/* BANK 1 */
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#define CONFIG 0
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#define CFG_AUI_SELECT 0x100
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#define BASE 2
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#define ADDR0 4
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#define ADDR1 6
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#define ADDR2 8
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#define GENERAL 10
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#define CONTROL 12
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#define CTL_POWERDOWN 0x2000
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#define CTL_LE_ENABLE 0x80
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#define CTL_CR_ENABLE 0x40
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#define CTL_TE_ENABLE 0x0020
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#define CTL_AUTO_RELEASE 0x0800
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#define CTL_EPROM_ACCESS 0x0003 /* high if Eprom is being read */
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/* BANK 2 */
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#define MMU_CMD 0
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#define MC_BUSY 1 /* only readable bit in the register */
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#define MC_NOP 0
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#define MC_ALLOC 0x20 /* or with number of 256 byte packets */
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#define MC_RESET 0x40
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#define MC_REMOVE 0x60 /* remove the current rx packet */
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#define MC_RELEASE 0x80 /* remove and release the current rx packet */
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#define MC_FREEPKT 0xA0 /* Release packet in PNR register */
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#define MC_ENQUEUE 0xC0 /* Enqueue the packet for transmit */
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#define PNR_ARR 2
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#define FIFO_PORTS 4
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#define FP_RXEMPTY 0x8000
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#define FP_TXEMPTY 0x80
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#define POINTER 6
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#define PTR_READ 0x2000
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#define PTR_RCV 0x8000
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#define PTR_AUTOINC 0x4000
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#define PTR_AUTO_INC 0x0040
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#define DATA_1 8
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#define DATA_2 10
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#define INTERRUPT 12
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#define INT_MASK 13
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#define IM_RCV_INT 0x1
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#define IM_TX_INT 0x2
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#define IM_TX_EMPTY_INT 0x4
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#define IM_ALLOC_INT 0x8
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#define IM_RX_OVRN_INT 0x10
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#define IM_EPH_INT 0x20
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#define IM_ERCV_INT 0x40 /* not on SMC9192 */
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/* BANK 3 */
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#define MULTICAST1 0
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#define MULTICAST2 2
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#define MULTICAST3 4
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#define MULTICAST4 6
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#define MGMT 8
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#define REVISION 10 /* ( hi: chip id low: rev # ) */
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/* this is NOT on SMC9192 */
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#define ERCV 12
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#define CHIP_9190 3
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#define CHIP_9194 4
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#define CHIP_9195 5
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#define CHIP_91100 7
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static const char * chip_ids[ 15 ] = {
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NULL, NULL, NULL,
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/* 3 */ "SMC91C90/91C92",
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/* 4 */ "SMC91C94",
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/* 5 */ "SMC91C95",
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NULL,
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/* 7 */ "SMC91C100",
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/* 8 */ "SMC91C100FD",
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NULL, NULL, NULL,
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NULL, NULL, NULL};
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/*
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. Transmit status bits
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*/
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#define TS_SUCCESS 0x0001
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#define TS_LOSTCAR 0x0400
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#define TS_LATCOL 0x0200
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#define TS_16COL 0x0010
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/*
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. Receive status bits
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*/
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#define RS_ALGNERR 0x8000
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#define RS_BADCRC 0x2000
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#define RS_ODDFRAME 0x1000
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#define RS_TOOLONG 0x0800
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#define RS_TOOSHORT 0x0400
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#define RS_MULTICAST 0x0001
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#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
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static const char * interfaces[ 2 ] = { "TP", "AUI" };
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/*-------------------------------------------------------------------------
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. I define some macros to make it easier to do somewhat common
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. or slightly complicated, repeated tasks.
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--------------------------------------------------------------------------*/
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/* select a register bank, 0 to 3 */
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#define SMC_SELECT_BANK(x) { outw( x, ioaddr + BANK_SELECT ); }
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/* define a small delay for the reset */
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#define SMC_DELAY() { inw( ioaddr + RCR );\
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inw( ioaddr + RCR );\
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inw( ioaddr + RCR ); }
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/* this enables an interrupt in the interrupt mask register */
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#define SMC_ENABLE_INT(x) {\
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unsigned char mask;\
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SMC_SELECT_BANK(2);\
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mask = inb( ioaddr + INT_MASK );\
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mask |= (x);\
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outb( mask, ioaddr + INT_MASK ); \
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}
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/* this disables an interrupt from the interrupt mask register */
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#define SMC_DISABLE_INT(x) {\
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unsigned char mask;\
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SMC_SELECT_BANK(2);\
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mask = inb( ioaddr + INT_MASK );\
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mask &= ~(x);\
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outb( mask, ioaddr + INT_MASK ); \
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}
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/*----------------------------------------------------------------------
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. Define the interrupts that I want to receive from the card
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.
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. I want:
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. IM_EPH_INT, for nasty errors
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. IM_RCV_INT, for happy received packets
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. IM_RX_OVRN_INT, because I have to kick the receiver
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--------------------------------------------------------------------------*/
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#define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT)
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#endif /* _SMC_9194_H_ */
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