mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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8f318526a2
Commit1a1ebd5("irqchip/gic-v3: Make sure read from ICC_IAR1_EL1 is visible on redestributor") fixed the missing barrier on arm64, but forgot to update the 32bit counterpart, which has the same requirements. Let's fix it. Fixes:1a1ebd5("irqchip/gic-v3: Make sure read from ICC_IAR1_EL1 is visible on redestributor") Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
191 lines
5.2 KiB
C
191 lines
5.2 KiB
C
/*
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* arch/arm/include/asm/arch_gicv3.h
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*
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* Copyright (C) 2015 ARM Ltd.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_ARCH_GICV3_H
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#define __ASM_ARCH_GICV3_H
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#ifndef __ASSEMBLY__
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#include <linux/io.h>
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#include <asm/barrier.h>
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#define __ACCESS_CP15(CRn, Op1, CRm, Op2) p15, Op1, %0, CRn, CRm, Op2
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#define __ACCESS_CP15_64(Op1, CRm) p15, Op1, %Q0, %R0, CRm
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#define ICC_EOIR1 __ACCESS_CP15(c12, 0, c12, 1)
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#define ICC_DIR __ACCESS_CP15(c12, 0, c11, 1)
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#define ICC_IAR1 __ACCESS_CP15(c12, 0, c12, 0)
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#define ICC_SGI1R __ACCESS_CP15_64(0, c12)
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#define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0)
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#define ICC_CTLR __ACCESS_CP15(c12, 0, c12, 4)
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#define ICC_SRE __ACCESS_CP15(c12, 0, c12, 5)
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#define ICC_IGRPEN1 __ACCESS_CP15(c12, 0, c12, 7)
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#define ICC_HSRE __ACCESS_CP15(c12, 4, c9, 5)
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#define ICH_VSEIR __ACCESS_CP15(c12, 4, c9, 4)
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#define ICH_HCR __ACCESS_CP15(c12, 4, c11, 0)
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#define ICH_VTR __ACCESS_CP15(c12, 4, c11, 1)
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#define ICH_MISR __ACCESS_CP15(c12, 4, c11, 2)
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#define ICH_EISR __ACCESS_CP15(c12, 4, c11, 3)
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#define ICH_ELSR __ACCESS_CP15(c12, 4, c11, 5)
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#define ICH_VMCR __ACCESS_CP15(c12, 4, c11, 7)
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#define __LR0(x) __ACCESS_CP15(c12, 4, c12, x)
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#define __LR8(x) __ACCESS_CP15(c12, 4, c13, x)
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#define ICH_LR0 __LR0(0)
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#define ICH_LR1 __LR0(1)
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#define ICH_LR2 __LR0(2)
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#define ICH_LR3 __LR0(3)
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#define ICH_LR4 __LR0(4)
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#define ICH_LR5 __LR0(5)
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#define ICH_LR6 __LR0(6)
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#define ICH_LR7 __LR0(7)
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#define ICH_LR8 __LR8(0)
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#define ICH_LR9 __LR8(1)
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#define ICH_LR10 __LR8(2)
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#define ICH_LR11 __LR8(3)
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#define ICH_LR12 __LR8(4)
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#define ICH_LR13 __LR8(5)
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#define ICH_LR14 __LR8(6)
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#define ICH_LR15 __LR8(7)
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/* LR top half */
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#define __LRC0(x) __ACCESS_CP15(c12, 4, c14, x)
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#define __LRC8(x) __ACCESS_CP15(c12, 4, c15, x)
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#define ICH_LRC0 __LRC0(0)
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#define ICH_LRC1 __LRC0(1)
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#define ICH_LRC2 __LRC0(2)
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#define ICH_LRC3 __LRC0(3)
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#define ICH_LRC4 __LRC0(4)
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#define ICH_LRC5 __LRC0(5)
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#define ICH_LRC6 __LRC0(6)
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#define ICH_LRC7 __LRC0(7)
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#define ICH_LRC8 __LRC8(0)
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#define ICH_LRC9 __LRC8(1)
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#define ICH_LRC10 __LRC8(2)
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#define ICH_LRC11 __LRC8(3)
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#define ICH_LRC12 __LRC8(4)
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#define ICH_LRC13 __LRC8(5)
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#define ICH_LRC14 __LRC8(6)
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#define ICH_LRC15 __LRC8(7)
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#define __AP0Rx(x) __ACCESS_CP15(c12, 4, c8, x)
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#define ICH_AP0R0 __AP0Rx(0)
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#define ICH_AP0R1 __AP0Rx(1)
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#define ICH_AP0R2 __AP0Rx(2)
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#define ICH_AP0R3 __AP0Rx(3)
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#define __AP1Rx(x) __ACCESS_CP15(c12, 4, c9, x)
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#define ICH_AP1R0 __AP1Rx(0)
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#define ICH_AP1R1 __AP1Rx(1)
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#define ICH_AP1R2 __AP1Rx(2)
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#define ICH_AP1R3 __AP1Rx(3)
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/* Low-level accessors */
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static inline void gic_write_eoir(u32 irq)
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{
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asm volatile("mcr " __stringify(ICC_EOIR1) : : "r" (irq));
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isb();
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}
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static inline void gic_write_dir(u32 val)
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{
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asm volatile("mcr " __stringify(ICC_DIR) : : "r" (val));
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isb();
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}
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static inline u32 gic_read_iar(void)
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{
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u32 irqstat;
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asm volatile("mrc " __stringify(ICC_IAR1) : "=r" (irqstat));
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dsb(sy);
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return irqstat;
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}
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static inline void gic_write_pmr(u32 val)
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{
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asm volatile("mcr " __stringify(ICC_PMR) : : "r" (val));
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}
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static inline void gic_write_ctlr(u32 val)
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{
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asm volatile("mcr " __stringify(ICC_CTLR) : : "r" (val));
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isb();
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}
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static inline void gic_write_grpen1(u32 val)
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{
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asm volatile("mcr " __stringify(ICC_IGRPEN1) : : "r" (val));
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isb();
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}
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static inline void gic_write_sgi1r(u64 val)
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{
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asm volatile("mcrr " __stringify(ICC_SGI1R) : : "r" (val));
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}
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static inline u32 gic_read_sre(void)
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{
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u32 val;
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asm volatile("mrc " __stringify(ICC_SRE) : "=r" (val));
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return val;
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}
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static inline void gic_write_sre(u32 val)
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{
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asm volatile("mcr " __stringify(ICC_SRE) : : "r" (val));
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isb();
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}
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/*
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* Even in 32bit systems that use LPAE, there is no guarantee that the I/O
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* interface provides true 64bit atomic accesses, so using strd/ldrd doesn't
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* make much sense.
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* Moreover, 64bit I/O emulation is extremely difficult to implement on
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* AArch32, since the syndrome register doesn't provide any information for
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* them.
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* Consequently, the following IO helpers use 32bit accesses.
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*
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* There are only two registers that need 64bit accesses in this driver:
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* - GICD_IROUTERn, contain the affinity values associated to each interrupt.
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* The upper-word (aff3) will always be 0, so there is no need for a lock.
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* - GICR_TYPER is an ID register and doesn't need atomicity.
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*/
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static inline void gic_write_irouter(u64 val, volatile void __iomem *addr)
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{
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writel_relaxed((u32)val, addr);
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writel_relaxed((u32)(val >> 32), addr + 4);
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}
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static inline u64 gic_read_typer(const volatile void __iomem *addr)
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{
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u64 val;
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val = readl_relaxed(addr);
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val |= (u64)readl_relaxed(addr + 4) << 32;
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return val;
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}
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#endif /* !__ASSEMBLY__ */
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#endif /* !__ASM_ARCH_GICV3_H */
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