mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-24 00:40:51 +07:00
302 lines
9.0 KiB
C
302 lines
9.0 KiB
C
#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kthread.h>
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#include <linux/pci.h>
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MODULE_LICENSE("Proprietary");
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#define SYNO_JMB585_PORT_NUM 5
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#define SYNO_JMB582_PORT_NUM 2
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const unsigned jmb_port_addr[3][SYNO_JMB585_PORT_NUM] = {{0x74, 0x76, 0x78, 0x7A, 0x7C},
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{0x73, 0x75, 0x77, 0x79, 0x7B},
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{0x04, 0x11, 0x1e, 0x2b, 0x38}};
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const unsigned jmb_port_ctle_reg[SYNO_JMB585_PORT_NUM] = {0x0B, 0x18, 0x25, 0x32, 0x3F};
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const unsigned jmb_ssc_addr = 0x2;
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static void syno_jmb_read_phy_reg(void __iomem *bar5, u32 addr, u32 *data, unsigned long reg_type)
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{
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// Index port has 24 bits, PHY registers access uses bit[12:0] and bit[18], bit[18] is used to select:
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// 0: PCIe PHY registers.
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// 1: SATA PHY registers.
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// Offset C0 [IDXP] is index port register
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writel((addr & 0x01FFFUL) + (reg_type << 18UL), bar5 + 0xC0);
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// Offset C8 [DPHY] is data port for PCIe/SATA PHY registers access.
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*data = readl(bar5 + 0xC8);
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}
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static int syno_jmb_sata_check(unsigned pID, int portNum)
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{
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struct pci_dev *pdev = NULL;
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void __iomem *bar5 = NULL;
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u32 value = 0;
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int i = 0;
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int j = 0;
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int iRet = -1;
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unsigned long reg_type = 0; //read sata register or pcie register, 1 for sata, 0 for pcie
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printk("======= JMicron %x =======\n", pID);
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while ((pdev = pci_get_device(0x197b, pID, pdev)) != NULL) {
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bar5 = ioremap(pci_resource_start(pdev, 5), pci_resource_len(pdev, 5));
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if (!bar5) {
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printk("Can't map jmb%x registers pci%d:%d\n", pID, pdev->bus->number, pdev->bus->primary);
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goto END;
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}
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//check pcie register
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reg_type = 0; // 0 for pcie phy register
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syno_jmb_read_phy_reg(bar5, 0x1035, &value, reg_type);// 0x00000001 1: enable, 0: disable
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printk("pci %d:%d Preset %s\n", pdev->bus->number, pdev->bus->primary, (value & 0x00000001)?"Enable":"Disable");
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syno_jmb_read_phy_reg(bar5, 0x1034, &value, reg_type);// 0x00000044 preset value, lane0/1 preset = 0x4
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printk("pci %d:%d Preset Value: 0x%x\n", pdev->bus->number, pdev->bus->primary, value);
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syno_jmb_read_phy_reg(bar5, 0x28, &value, reg_type); // 0x222A90F3 // PCIe impedance
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printk("pci %d:%d PCIe impedance reg: 0x%x\n", pdev->bus->number, pdev->bus->primary, value);
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syno_jmb_read_phy_reg(bar5, 0x428, &value, reg_type); // 0x222A90F3 // PCIe impedance
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printk("pci %d:%d PCIe impedance reg: 0x%x\n", pdev->bus->number, pdev->bus->primary, value);
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//check sata register
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reg_type = 1; // 1 for sata phy register
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syno_jmb_read_phy_reg(bar5, jmb_ssc_addr, &value, reg_type); //
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printk("pci %d:%d SSC reg: 0x%x, SSC %s\n", pdev->bus->number, pdev->bus->primary, value, (value & 0x00000010)?"off":"on");
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//check sata signal
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for (i = 0 ; i < portNum; i++) {
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for (j = 0 ; j < 3; j++) {
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syno_jmb_read_phy_reg(bar5, jmb_port_addr[j][i], &value, reg_type);
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printk("pci %d:%d port %d gen %d: %x\n",pdev->bus->number, pdev->bus->primary, i, j + 1, value);
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}
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syno_jmb_read_phy_reg(bar5, jmb_port_ctle_reg[i], &value, reg_type);
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printk("pci %d:%d port %d SATA CTLE : 0x%x\n",pdev->bus->number, pdev->bus->primary, i, value);
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}
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if (bar5) {
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iounmap(bar5);
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bar5 = NULL;
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}
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}
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printk("============================\n");
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iRet = 0;
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END:
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return iRet;
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}
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const unsigned mv_port_gen[3] = {0x8D, 0x8F, 0x91};
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const unsigned mv_port_addr[4] = {0x178, 0x1f8, 0x278, 0x2f8};
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const unsigned mv_port_data[4] = {0x17c, 0x1fc, 0x27c, 0x2fc};
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static int syno_mv_sata_check(unsigned pID, int portNum)
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{
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struct pci_dev *pdev = NULL;
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void __iomem *bar5 = NULL;
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u32 value = 0;
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int i = 0;
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int j = 0;
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int iRet = -1;
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printk("======= Marvell %x =======\n", pID);
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while ((pdev = pci_get_device(0x1b4b, pID, pdev)) != NULL) {
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bar5 = ioremap(pci_resource_start(pdev, 5), pci_resource_len(pdev, 5));
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if (!bar5) {
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printk("Can't map mv%x registers pci%d:%d\n", pID, pdev->bus->number, pdev->bus->primary);
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goto END;
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}
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for (i = 0 ; i < portNum; i++) {
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for (j = 0; j < 3; j++) {
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writel(mv_port_gen[j], bar5 + mv_port_addr[i]);
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value = readl(bar5 + mv_port_data[i]);
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printk("pci %d:%d port %d gen %d: %x\n",pdev->bus->number, pdev->bus->primary, i, j + 1 ,value);
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}
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}
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if (bar5) {
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iounmap(bar5);
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bar5 = NULL;
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}
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}
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printk("============================\n");
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iRet = 0;
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END:
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return iRet;
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}
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const unsigned asmedia_1061_gen[3] = {0x4, 0x5, 0x6};
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const unsigned asmedia_1061_addr[2] = {0xCA0, 0xDA0};
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const unsigned asmedia_116x_port_addr[3][6] = {{0x122, 0x322, 0x522, 0x722, 0x922, 0xB22},
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{0x123, 0x323, 0x523, 0x723, 0x923, 0xB23},
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{0x124, 0x324, 0x524, 0x724, 0x924, 0xB24}};
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const unsigned asmedia_116x_ssc_addr = 0x198C;
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static int syno_asm1061_sata_check(unsigned pID, int portNum)
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{
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struct pci_dev *pdev = NULL;
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u8 value = 0;
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unsigned int devfn = 0;
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int i = 0;
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int j = 0;
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int iRet = -1;
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devfn = PCI_DEVFN(0x00, 0x0);
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printk("======= Asmedia 1061 =======\n");
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while ((pdev = pci_get_device(0x1b21, pID, pdev)) != NULL) {
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for (i = 0 ; i < portNum; i++) {
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for (j = 0; j < 3; j++) {
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pci_bus_read_config_byte(pdev->bus, devfn, asmedia_1061_addr[i] | asmedia_1061_gen[j], &value);
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printk("pci %d:%d port %d gen %d: %x\n",pdev->bus->number, pdev->bus->primary, i, j + 1 ,value);
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}
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}
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}
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printk("============================\n");
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iRet = 0;
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return iRet;
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}
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static int syno_asm116x_sata_check(unsigned pID,int portNum)
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{
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struct pci_dev *pdev = NULL;
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void __iomem *bar0 = NULL;
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u8 reg_data = 0;
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int i = 0;
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int j = 0;
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int iRet = -1;
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printk("======= Asmedia %x =======\n", pID);
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while ((pdev = pci_get_device(0x1b21, pID, pdev)) != NULL) {
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bar0 = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
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if (!bar0) {
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printk("Can't map asm%x registers pci%d:%d\n", pID, pdev->bus->number, pdev->bus->primary);
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goto END;
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}
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//read SSC register
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reg_data = readb(bar0 + asmedia_116x_ssc_addr);
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printk("pci %d:%d SSC reg: 0x%x, SSC %s\n", pdev->bus->number, pdev->bus->primary, reg_data, (reg_data & 0x01)?"on":"off");
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for (i = 0 ; i < portNum; i++) {
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for (j = 0; j < 3; j++) {
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reg_data = readb(bar0 + asmedia_116x_port_addr[j][i]);
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printk("pci %d:%d port %d gen %d: %x\n",pdev->bus->number, pdev->bus->primary, i, j + 1 ,reg_data);
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}
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}
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if (bar0) {
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iounmap(bar0);
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bar0 = NULL;
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}
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}
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printk("============================\n");
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iRet = 0;
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END:
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return iRet;
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}
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typedef union u {
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u32 raw;
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struct u_fields{
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u8 byteen ;
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u8 Register ;
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u8 portid ;
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u8 opcode ;
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} field;
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} SideBandMsg_t ;
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#define UNCORE_REG_MCR 0xd0 // Message Control
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#define UNCORE_REG_MDR 0xd4 // Message Data
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#define UNCORE_REG_MER 0xd8 // Extended address or offset attributes
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int MsgPortRead(u8 Opcode, u8 Port, u32 Register, u32 *Data, u32 addr)
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{
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SideBandMsg_t readMsg;
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u32 Data32;
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Data32= Register & 0xFFFFFF00;
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readMsg.field.opcode = (u8) Opcode;
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readMsg.field.portid = (u8) Port;
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readMsg.field.byteen = (u8) 0xf0;
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if( Register > 255 ) { // needs other register to hold 8+ bits
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outl(addr + UNCORE_REG_MER, 0xCF8);
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outl(Data32, 0xCFC);
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readMsg.field.Register = (u8) Register ;
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}else {
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outl(addr + UNCORE_REG_MER, 0xCF8);
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outl(0, 0xCFC);
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readMsg.field.Register = (u8) Register ;
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};
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outl(addr + UNCORE_REG_MCR, 0xCF8);
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outl(readMsg.raw, 0xCFC);
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outl(addr + UNCORE_REG_MDR, 0xCF8);
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*Data = inl(0xCFC);
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return 0;
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}
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#define PCI_CONF1_ADDRESS(bus, devfn, reg) \
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(0x80000000 | ((reg & 0xF00) << 16) | (bus << 16) \
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| (devfn << 8) | (reg & 0xFC))
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static int intel_soc_sata(unsigned pID)
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{
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struct pci_dev *pdev = NULL;
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u32 value = 0;
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int i = 0;
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int j = 0;
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u32 offset_t = 0;
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unsigned int port[4]= {0x0, 0x200, 0x400, 0x600};
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unsigned int offset[6]= {0x88, 0x8c, 0x90, 0x100, 0x104, 0x108};
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u32 addr = 0;
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printk("======= Intel SoC SATA =======\n");
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while ((pdev = pci_get_device(0x8086, pID, pdev)) != NULL) {
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addr = PCI_CONF1_ADDRESS(0, pdev->devfn, 0);
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for (i = 0 ; i < 2; i++) {
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for (j = 0; j < 6; j++) {
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offset_t = port[i] + offset[j];
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MsgPortRead(0x0, 0x46, offset_t, &value, addr);
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printk("gen3 port[%x] offset[%x]=0x%x\n", i, j, value);
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}
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printk("\n");
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}
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for (i = 0 ; i < 4; i++) {
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for (j = 0; j < 6 ; j++) {
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offset_t = port[i] + offset[j];
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MsgPortRead(0x0, 0x43, offset_t, &value, addr);
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printk("gen2 port[%x] offset[%x]=0x%x\n", i, j, value);
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}
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printk("\n");
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}
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}
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return 0;
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}
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static int __init syno_sata_check_init(void)
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{
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syno_mv_sata_check(0x9235, 4);
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syno_mv_sata_check(0x9215, 4);
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syno_mv_sata_check(0x9170, 2);
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syno_asm1061_sata_check(0x0612, 2);
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syno_asm116x_sata_check(0x1164, 4);
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syno_jmb_sata_check(0x0585, SYNO_JMB585_PORT_NUM);
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syno_jmb_sata_check(0x0582, SYNO_JMB582_PORT_NUM);
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intel_soc_sata(0x1f0c);
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printk("Syno_SATA_check: Initialization completed.\n");
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return 0;
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}
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static void __exit syno_sata_check_exit(void)
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{
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return;
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}
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MODULE_AUTHOR("EricC");
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MODULE_DESCRIPTION("Syno_SATA_check\n");
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MODULE_LICENSE("Synology Inc.");
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module_init(syno_sata_check_init);
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module_exit(syno_sata_check_exit);
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