mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-24 02:20:54 +07:00
3b5015c4d8
The nand_clk is actually called the nand_x_clk and the parent is the l4_mp_clk, not the l4_main_clk. The nand_clk is a child of the nand_x_clk and has a fixed divider of 4. The same is true for the nand_ecc_clk. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
87 lines
2.5 KiB
C
87 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2017, Intel Corporation
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*/
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#ifndef __STRATIX10_CLOCK_H
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#define __STRATIX10_CLOCK_H
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/* fixed rate clocks */
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#define STRATIX10_OSC1 0
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#define STRATIX10_CB_INTOSC_HS_DIV2_CLK 1
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#define STRATIX10_CB_INTOSC_LS_CLK 2
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#define STRATIX10_F2S_FREE_CLK 3
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/* fixed factor clocks */
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#define STRATIX10_L4_SYS_FREE_CLK 4
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#define STRATIX10_MPU_PERIPH_CLK 5
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#define STRATIX10_MPU_L2RAM_CLK 6
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#define STRATIX10_SDMMC_CIU_CLK 7
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/* PLL clocks */
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#define STRATIX10_MAIN_PLL_CLK 8
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#define STRATIX10_PERIPH_PLL_CLK 9
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#define STRATIX10_BOOT_CLK 10
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/* Periph clocks */
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#define STRATIX10_MAIN_MPU_BASE_CLK 11
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#define STRATIX10_MAIN_NOC_BASE_CLK 12
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#define STRATIX10_MAIN_EMACA_CLK 13
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#define STRATIX10_MAIN_EMACB_CLK 14
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#define STRATIX10_MAIN_EMAC_PTP_CLK 15
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#define STRATIX10_MAIN_GPIO_DB_CLK 16
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#define STRATIX10_MAIN_SDMMC_CLK 17
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#define STRATIX10_MAIN_S2F_USR0_CLK 18
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#define STRATIX10_MAIN_S2F_USR1_CLK 19
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#define STRATIX10_MAIN_PSI_REF_CLK 20
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#define STRATIX10_PERI_MPU_BASE_CLK 21
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#define STRATIX10_PERI_NOC_BASE_CLK 22
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#define STRATIX10_PERI_EMACA_CLK 23
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#define STRATIX10_PERI_EMACB_CLK 24
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#define STRATIX10_PERI_EMAC_PTP_CLK 25
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#define STRATIX10_PERI_GPIO_DB_CLK 26
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#define STRATIX10_PERI_SDMMC_CLK 27
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#define STRATIX10_PERI_S2F_USR0_CLK 28
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#define STRATIX10_PERI_S2F_USR1_CLK 29
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#define STRATIX10_PERI_PSI_REF_CLK 30
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#define STRATIX10_MPU_FREE_CLK 31
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#define STRATIX10_NOC_FREE_CLK 32
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#define STRATIX10_S2F_USR0_CLK 33
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#define STRATIX10_NOC_CLK 34
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#define STRATIX10_EMAC_A_FREE_CLK 35
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#define STRATIX10_EMAC_B_FREE_CLK 36
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#define STRATIX10_EMAC_PTP_FREE_CLK 37
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#define STRATIX10_GPIO_DB_FREE_CLK 38
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#define STRATIX10_SDMMC_FREE_CLK 39
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#define STRATIX10_S2F_USER1_FREE_CLK 40
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#define STRATIX10_PSI_REF_FREE_CLK 41
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/* Gate clocks */
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#define STRATIX10_MPU_CLK 42
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#define STRATIX10_L4_MAIN_CLK 43
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#define STRATIX10_L4_MP_CLK 44
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#define STRATIX10_L4_SP_CLK 45
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#define STRATIX10_CS_AT_CLK 46
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#define STRATIX10_CS_TRACE_CLK 47
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#define STRATIX10_CS_PDBG_CLK 48
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#define STRATIX10_CS_TIMER_CLK 49
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#define STRATIX10_S2F_USER0_CLK 50
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#define STRATIX10_S2F_USER1_CLK 51
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#define STRATIX10_EMAC0_CLK 52
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#define STRATIX10_EMAC1_CLK 53
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#define STRATIX10_EMAC2_CLK 54
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#define STRATIX10_EMAC_PTP_CLK 55
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#define STRATIX10_GPIO_DB_CLK 56
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#define STRATIX10_SDMMC_CLK 57
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#define STRATIX10_PSI_REF_CLK 58
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#define STRATIX10_USB_CLK 59
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#define STRATIX10_SPI_M_CLK 60
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#define STRATIX10_NAND_CLK 61
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#define STRATIX10_NAND_X_CLK 62
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#define STRATIX10_NAND_ECC_CLK 63
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#define STRATIX10_NUM_CLKS 64
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#endif /* __STRATIX10_CLOCK_H */
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